Semiconductor Device And Production Method For Semiconductor Device

ABSTRACT

A power semiconductor device in which a semiconductor element is die-mount-connected onto a lead frame in a Pb-free manner. In a die-mount-connection with a large difference of thermal expansion coefficient between a semiconductor element  1  and a lead frame  2 , the connection is made with an intermetallic compound  200  having a melting point of 260° C. or higher or a Pb-free solder having a melting point of 260° C. or higher to 400° C. or lower, at the same time, the thermal stress produced in temperature cycles is buffered by a metal layer  100  having a melting point of 260° C. or higher. A Pb-free die-mount-connection which does not melt at the time of reflowing but have no chip crack to occur according to thermal stress can be achieved.

TECHNICAL FIELD

The present invention relates to a semiconductor device technologyincluding a power semiconductor device having a die-mount-connectionpart connected with the use of a Pb(lead)-free metal composite foil.

BACKGROUND ART

A conventional power semiconductor device is shown in FIG. 1 wherein apower semiconductor element 1 a is die-mount-connected onto a lead frame2 by means a solder 3. After bonding the resulting product to leads 5through wires 4, respectively, the bonded product is resin-molded withan epoxy-based resin 6. In this case, a high Pb solder and a solder towhich trace amount of Ag or Cu are added to have a melting point(solidus temperature) of 290° C. or higher are used as the solder 3.

In the wire bonding process, there is a case where the temperaturebecomes 280° C. at the maximum. Furthermore, when a power semiconductordevice is surface-mount soldered to a substrate, it is supposed that thepower semiconductor is heated up to 260° C. at the highest in the caseof reflow connection, since the melting point of a Sn—Ag—Cu based Pbfree solder which will be used typically hereafter is high, i.e. about220° C. Accordingly, a solder having a melting point of higher than 280°C., i.e. the above-mentioned high Pb solder is used in such that thesolder 3 does not remelt in the case of wire bonding and in the case ofreflowing.

In the case of wire bonding, when the solder is remelted, the wirebonding becomes impossible. Although the solder-connected part of thepower semiconductor element 1 a and the lead frame 2 has beenresin-molded with the epoxy-based resin 6, when the solder 3 inside theresin mold remelts, there arises a case where the solder 3 existinginside the resin mold leaks out from the interface of the epoxy-basedresin 6 and the lead frame 2, because of the cubical expansion due tothe melting phenomenon which is called by the name of “flash” as shownin FIG. 2. Even if the solder 3 did not leak out, it behaves to leak outso that large voids are formed in the solder 3 after the solidificationthereof, whereby it causes the device to be defective.

The soldered portion of the die-mount-connected part does not mean onlyfor fixing the power semiconductor element 1 a to the lead frame 2, butit functions as a path for escaping the heat of the power semiconductorelement 1 a to the lead frame 2 side. For this reason, when the voidsand the like are formed due to remelting of the solder 3 as describedabove, it becomes that diffusion of the heat is not sufficientlyperformed through the connection part, resulting in functionaldeterioration of the power semiconductor element 1 a.

As a result of decision of the enforcement of ROHS Directive (therestriction of the use of certain hazardous substances in electrical andelectronic equipment) by EU dated Jul. 1, 2006, a project for makingsolder for connection with respect to a substrate to be lead-freeadvances rapidly with focusing on Sn—Ag—Cu based Pb-free solders.

On the other hand, die-mount-connection wherein a high Pb solder hasbeen used heretofore is excluded from the object of the above-mentionedrestriction because no technical solution as to a replaceable solder ofa Pb-free solder is not found. It is, however, desired to make also suchhigh Pb solder to be Pb-free in view of reduction of environmentalburdens.

However, in the Pb-free solder to be used in a die-mount-connectionpart, it is required to have a high melting point at which the Pb-freesolder does not remelt in the case of wire bonding or in the case ofreflowing in board-mounting as mentioned above. Concerning wire bonding,it is possible to change the wire bonding to a bonding at a lowtemperature such as ultrasonic bonding of Al at a room temperature.However, reflow soldering on the substrate to which a Sn—Ag—Cu-basedPb-free solder is applied is an unavoidable process, so that it isrequired to make a melting point of the solder 3 to be at least 260° C.or higher.

Among Sn-based Pb-free solders, there are Sn—Sb-based solders (a meltingpoint of 232 to 240° C.) as those having comparatively high meltingpoints. However, even in such melting points, they are too low so thatthey cannot be applied because of remelting in the post-process.

In addition, Au-20Sn (melting point: 280° C.) is well known as a Pb-freehigh-melting point solder. However, since it contains 80% of Au, it isexpensive so that it is difficult to apply to inexpensive electronicparts from the viewpoint of the cost. Furthermore, since the Au-20Snsolder is a hard solder having rigidity, there is a fear of damaging thepower semiconductor element or the connection part, resulting in aproblem of connection reliability in such a case where the followingcondition for application of the Au-20Sn solder wherein thermal fatigueare experienced repeatedly under an insufficient stress bufferingfunction is supposed for applying to die-mount connection wherein theconnection is made in a comparatively large area in a combination ofpresenting such a large thermal expansion coefficient difference in thepower semiconductor element (Si) and a Cu-based frame.

Such problems of the connection reliability may be improved byincreasing the solder supply, but on the other hand, the increasedsupply results in a further expensive cost, whereby a problem ofprofitability arises.

On the other hand, such a challenge that the connection part is made tobe an alloy in the case of realizing a Pb-free state of the connectionpart is reported in non-patent document 1.

Namely, it is reported that the GaAs the rear surface thereof ismetallized with Cr (0.03 μm)/Sn (2.5 μm)/Cu (0.1 μm) is connected with asubstrate (glass) metallized with Cr (0.03 μm)/Cu (4.4 μm)/Au (0.1 μm)at 280° C., and then, it is maintained for 16 hours, whereby theconnection part is made to be substantially Cu₃Sn compound, so that itbecomes possible to make the connection part to have a high meltingpoint.

Likewise, it is reported that the Si the rear surface thereof ismetallized with Cr (0.03 μm)/In (3.0 μm)/Ag (0.5 μm) is connected withthe Si metallized with Cr (0.03 μm)/Au (0.05 μm)/Ag (5.5 μm)/Au (0.05μm) at 210° C., and then, it is subjected to aging treatment at 150° C.for 24 hours, whereby the connection part is made to be Ag-richalloy+Ag₃In, so that it becomes possible to make the connection part tohave a high melting point.

In non-patent document 2, it is reported below in such that Ni-xCo(x=0.10) metallized with Sn-3.5Ag (26 μm) and a product obtained by thecovar metallized with Ni-20Co (5 μm) further metallized with Au (1 μm)are connected at 240° C. in such that they are fit together; and theyare maintained for 30 minutes, whereby the whole connection part is madeto be a (Ni, Co)Sn₂+(Ni, Co)₃Sn₄ compound, so that it becomes possibleto make the connection part to have a high melting point. In this case,growth rate of the compound is accelerated by using the Ni-20Cocontaining Co for the metallization.

In these methods, when the connection part was once made completely tohave a high melting point, the connection part is not remelted, but itis possible to hold the connection, even if the connection part isheated up to 260° C. in the case of reflow soldering.

Non-patent document 1: Williams W. So et al., “High Temperature JointsManufactured at Low Temperature”, Proceeding of ECTC; 1998, p 284.

Non-patent document 2: Yamamoto et al., “Study for makingmicro-connection part using Sn—Ag solder to be intermetallic compound”,Collection of Brief Summary of MES 2003; October 2003, p 45.

DISCLOSURE OF THE INVENTION

The present inventors considered that the technologies for making amaterial to have a high melting point described in the non-patentdocuments 1 and 2 may be applied to obtain a Pb-free condition in adie-mount-connection part. In the above-described two prior arts,however, there is no consideration as to the following points, so thatit is difficult to apply the above-described technologies to thedie-mount-connection part where is required to have high connectionreliability for realizing an important function as a heat dissipationpath for a power semiconductor element.

More specifically, according to the connection methods of Williams W. Soet al. as well as Yamamoto et al., the connection part is made to be acompound so as to achieve a high melting point. As a result, theconnection part becomes rigid and brittle as compared with the existinghigh Pb solder. In this respect, however, the connection is conducted inthe combination of materials having a small difference in thecoefficients of thermal expansion in both the non-patent documents 1 and2. Accordingly, there is no consideration as to the damages and the likein the case where thermal fatigue is inflicted to the materials due tothe brittleness accompanied with such modification for achievingrealization of a high melting point.

In the case where the technologies of the non-patent documents 1 and 2are applied to the junction of the combination of the powersemiconductor element (Si) being the object of the present invention anda Cu-based lead frame exhibiting a large thermal expansion coefficientdifference, the hard and brittle connection part as shown in thenon-patent documents 1 and 2 cannot buffer the thermal stress producedin temperature cycles, resulting in a large load with respect to thechip thereby to cause chip cracks, and thus, the connection reliabilitycannot be assured.

Although it may be considered that a thickness of the connection part isincreased as the measure for improving the prevention of chip cracks,the thickened connection part brings about a very long period of timefor achieving a complete compound. In this respect, it is possible toincrease the connection temperature thereby to make faster the growthrate of the compound, so that the time required for achieving thecomplete compound can be reduced. In this case, however, the remainingstress after the connection becomes large, and hence, it becomes a causefor generating chip cracks.

As mentioned above, the technologies for achieving a high melting pointdescribed in the non-patent documents 1 and 2 cannot satisfy requiredspecifications in the die-mount-connection part in the existingcondition. Accordingly, it cannot be intended to apply the Pb-freetechnology to such die-mount-connection part as long as the problems ofsuch connection reliability are not solved.

An object of the present invention is to realize a Pb-free junctionwherein the connection may be maintained in the materials to be joinedsuch as a semiconductor element (Si) and a Cu-based lead frame whichexhibit a large thermal expansion coefficient difference thereof at eventhe highest temperature supposed to be in the case of reflowing, and bywhich the connection reliability causing no damage on the semiconductorelement with respect to thermal stress to the connection part can beassured.

Another object of the invention is to provide a Pb-free semiconductordevice by which the connection can be maintained in the case ofreflowing at 260° C., and good connection reliability can be attained inthe combination of materials such as a semiconductor element (Si) and aCu-based lead frame which exhibit a large thermal expansion coefficientdifference of them even in the case where die-mount-connection isconducted over a comparatively large area.

In order to solve the above-described problems, the present firstinvention provides a semiconductor device wherein a semiconductorelement is die-mount-connected onto a lead frame by means of a metaljoint, characterized in that the metal joint includes a stress bufferinglayer for buffering thermal stress produced due to a thermal expansioncoefficient difference between the lead frame and the semiconductorelement; a connection layer formed on the semiconductor element side ofthe stress buffering layer and for connecting the stress buffering layerwith the semiconductor element; and another connection layer formed onthe lead frame side of the stress buffering layer and for connecting thestress buffering layer with the lead frame.

The chip cracks appeared on the semiconductor element side in thedie-mount joint section is due to such fact that since a thermalexpansion coefficient difference between the lead frame to be jointedand the semiconductor element is large, the semiconductor element sidecannot expand and contract in response to that of the lead frame sidehaving a high thermal expansion coefficient. In this respect, when thestress buffering layer as described above is provided, the stress due tothermal expansion and contraction can be absorbed by the stressbuffering layer, whereby such stress is not transmitted to thesemiconductor element side, so that any chip crack does not appear.

A present second invention provides the semiconductor device asdescribed in the first invention, characterized in that the connectionlayer is a metal layer or an intermetallic compound layer having amelting point of 260° C. or higher; and the stress buffering layer is ametal layer having a thermal expansion coefficient ranging from thethermal expansion coefficient of the semiconductor element to thethermal expansion coefficient of the lead frame. When the thermalexpansion coefficient of the metal layer constituting the stressbuffering layer is set out as in the second invention, the stressderived from the lead frame side may be buffered.

A present third invention provides the semiconductor device as describedin the first invention, characterized in that the connection layer is ametal layer or an intermetallic compound layer having a melting point of260° C. or higher; and the stress buffering layer is a metal layerhaving an yield stress of less than 100 MPa. When the yield stress ofthe metal layer constituting the stress buffering layer is set out as inthe third invention, the stress derived from the lead frame side may bebuffered.

A present fourth invention provides the semiconductor device asdescribed in the first invention, characterized in that the connectionlayer formed on the semiconductor element side of the stress bufferinglayer is made of a Pb-free solder layer, for example, an Au—Sn-basedalloy, an Au—Ge-based alloy, an Au—Si-based alloy, a Zn—Al-based alloy,a Zn—Al—Ge-based alloy, Bi, a Bi—Ag-based alloy, a Bi—Cu-based alloy, aBi—Ag—Cu-based alloy or the like, having a melting point of 260° C. orhigher to 400° C. or lower; and the connection layer formed on the leadframe side of the stress buffering layer is made of a Pb-free solderlayer having a melting point of 260° C. or higher to 400° C. or lower,lower than that of the connection layer formed on the semiconductorelement side of the stress buffering layer.

As mentioned above, the chip cracks appeared on the semiconductorelement side in the die-mount joint section is due to such fact thatsince a thermal expansion coefficient difference between the lead frameto be joined and the semiconductor element is large, the semiconductorelement side cannot expand and contract in response to that of the leadframe side having a high thermal expansion coefficient. It may beconsidered to be possible to suppress such chip crack by increasing athickness of the metal joint section. In this respect, however, therearises such a problem that an Au-20Sn solder is expensive in the case ofthe connection with a single material, while sufficient heat dissipationcannot be made by a Bi-based solder because the thermal conductivitythereof is 9 W/m·K being as low as about ⅓ of a high Pb solder. On theother hand, when the metal joint section is made to be a completecompound, the joint section becomes rigid and brittle, besidesconsiderable time is required for achieving the complete compound, sothat there arises such a problem that the technology mentioned herein isdifficult to apply industrially from the viewpoint of productionefficiency.

Accordingly, when the stress buffering layer is provided as mentionedabove, the metal joint section may be thickened with the stressbuffering layer and the connection layer itself may be thinned. As aresult, an amount of the Au-20Sn to be applied can be reduced by theamount corresponding to the thinned layer, resulting in easier heatdissipation with the Bi-based solder having a low thermal conductivityin a degree corresponding to the thinned layer, so that an amount of arigid and brittle intermetallic compound may be reduced.

Thus, it becomes possible to join materials having a thermal expansioncoefficient difference to each other without accompanying any chip crackwithin a range wherein a difference of coefficients of thermal expansionextends from a small difference of, for example, about 4 ppm/° C. as inthe case of between Si and a ceramic substrate to a large difference ofabout 14 ppm/° C. as in the case of between Si and Cu as a result ofproviding the stress buffering layer.

The reason for employing a Pb-free solder having a melting point of 260°C. or higher to 400° C. or lower in the forth invention is in that thereare such a problem that a solder is remelted in the case of reflowsoldering, when the melting point of the solder is 260° C. or lower, andsuch a problem that a Cu-based frame becomes softened to be deformed inthe case of the die-mount-connection, when the melting point of thesolder is 400° C. or higher.

Furthermore, since it is possible to buffer thermal stress by means ofthe stress buffering layer, the reliability may be assured even in acase where the above-described Pb-free solder is thinly applied. Hence,it becomes possible to reduce an amount of a solder to be applied evenin a case where an expensive Au-based solder is used. In this case, athickness of a solder for the connection is preferably 1 μm or more.When it is less than 1 μm, the wettability over the whole region of theinterface cannot be assured in the case of the connection, and there maybe a case of poor connection.

In order to form connection layers on the semiconductor element side andthe lead frame side of the stress buffering layer, respectively, it mayapply, for instance, a composite foil containing metal layers which formthe connection layers by heating at the time of die-mount-connection ona metal layer having stress buffering function. As a result of providinga temperature stratum in the melting point of the connection layer onthe front and rear surfaces thereof, when the composite foil is suppliedto the lead frame at a temperature at which only the connection layerformed on the lead frame side of the stress buffering layer and apressurizing step as well as a scrubbing step are applied from the sideof the non-melting connection layer formed on the semiconductor elementside of the stress buffering layer, the connectability and the voidevacuatability can be improved in the connection part for composite foiland lead frame. In addition, when the pressurizing and scrubbing stepsare applied in the case of supplying the semiconductor element, theconnectability and the void evacuatability can be improved in thesemiconductor element and composite foil connection part as well.

A present fifth invention provides the semiconductor device as describedin the first invention, characterized in that the connection layerformed on the semiconductor element side of the stress buffering layeris made of a Pb-free solder layer, for example, an Au—Sn-based alloy, anAu—Ge-based alloy, an Au—Si-based alloy, a Zn—Al-based alloy, aZn—Al—Ge-based alloy, Bi, a Bi—Ag-based alloy, a Bi—Cu-based alloy, aBi—Ag—Cu-based alloy or the like, having a melting point of 260° C. orhigher to 400° C. or lower; and the connection layer formed on the leadframe side of the stress buffering layer is made of an intermetalliccompound layer having a melting point of 260° C. or higher and formed bythe reaction of at least one of Sn, In, Sn—Ag-based, Sn—Cu-based,Sn—Ag—Cu-based, Sn—Zn-based, Sn—Zn—Bi-based, Sn—In-based, In—Ag-based,In—Cu-based, Bi—Sn-based, Bi—In-based and the like Pb-free solders withat least one metal of Cu, Ag, Ni, and Au in the case of thedie-mount-connection.

In the case of die-mount-connection, when the connection is conducted ata temperature of 400° C. or higher, a Cu-based frame is softened, sothat it is necessary for conducting the connection at a temperature of400° C. or lower. Each of the Sn, In, Sn—Ag-based, Sn—Cu-based,Sn—Ag—Cu-based, Sn—Zn-based, Sn—Zn—Bi-based, Sn—In-based, In—Ag-based,In—Cu-based, Bi—Sn-based, Bi—In-based and the like Pb-free solders toform the connection layer made on the lead frame side of the stressbuffering layer has a melting point of 260° C. or lower. Accordingly,when any one of the above-described Pb-free solders is used alone forthe connection, the solder remelts in the case of reflow soldering,whereby the connection cannot be maintained due to solder flash andexfoliation in the connection interface.

Hence, it is necessary for making the melting point after the connectionto have a high melting point of 260° C. or higher as a result of theformation of a metal compound through the reaction of such a metal ofCu, Ag, Ni, or Au which reacts with any one of the Pb-free solders ofSn, In, Sn—Ag-based, Sn—Cu-based, Sn—Ag—Cu-based, Sn—Zn-based,Sn—Zn—Bi-based, Sn—In-based, In—Ag-based, In—Cu-based, Bi—Sn-based,Bi—In-based and the like. In this case, a thickness of the intermetalliccompound layer in the connection part is preferably 1 to 30 μm. When itis less than 1 μm, there may be a case where wettability cannot beassured over the whole region of the connection interface at the time ofthe connection, whereby poor connection arises. On the other hand, whenthe thickness is more than 30 μm, there may be a case where a longperiod of time is required for achieving the complete compound of theconnection part so that the productivity becomes poor. In addition,since the connection is possible at a temperature of 260° C. or lower,the residual stress appearing at the time of cooling after thedie-mount-connection can be reduced.

As a result of providing a temperature stratum in the melting point ofthe solder forming the connection layer on the front and rear surfacesof the composite foil, when the composite foil is supplied to the leadframe at a temperature at which only the connection layer formed on thelead frame side of the stress buffering layer and a pressurizing step aswell as a scrubbing step are applied from the side of the unmeltedconnection layer formed on the semiconductor element side of the stressbuffering layer, the connectability and the void evacuatability can beimproved in the connection part for composite foil and lead frame. Inaddition, when the pressurizing and scrubbing steps are applied in thecase of supplying the semiconductor element, the connectability and thevoid evacuatability can be improved also in the connection part for thesemiconductor element and composite foil. In this case, it is desiredthat the lead frame is connected with the composite foil by means of acompound even which is locally formed in the connection layer formed onthe lead frame side of the stress buffering layer.

A present sixth invention provides the semiconductor device as describedin the first invention, characterized in that the connection layerformed on the semiconductor element side of the stress buffering layeris made of an intermetallic compound layer having a melting point of260° C. or higher and formed by the reaction of one of Sn, In,Sn—Ag-based, Sn—Cu-based, Sn—Ag—Cu-based, Sn—Zn-based, Sn—Zn—Bi-based,Sn—In-based, In—Ag-based, In—Cu-based, Bi—Sn-based, Bi—In-based and thelike Pb-free solders each having a melting point of 260° C. or lowerwith at least one metal of Cu, Ag, Ni, and Au in the case of thedie-mount-connection; and the connection layer formed on the lead frameside of the stress buffering layer is made of an intermetallic compoundlayer having a melting point of 260° C. or higher and formed by thereaction of one of Sn, In, Sn—Ag-based, Sn—Cu-based, Sn—Ag—Cu-based,Sn—Zn-based, Sn—Zn—Bi-based, Sn—In-based, In—Ag-based, In—Cu-based,Bi—Sn-based, Bi—In-based and the like Pb-free solders each having alower melting point than that of the Pb-free solder forming theconnection layer formed on the semiconductor element side of the stressbuffering layer with at least one metal of Cu, Ag, Ni, and Au in thecase of the die-mount-connection.

In the case of die-mount-connection, when the connection is conducted ata temperature of 400° C. or higher, a Cu-based frame is softened, sothat it is necessary for conducting the connection at a temperature of400° C. or lower. Each of the Sn, In, Sn—Ag-based, Sn—Cu-based,Sn—Ag—Cu-based, Sn—Zn-based, Sn—Zn—Bi-based, Sn—In-based, In—Ag-based,In—Cu-based, Bi—Sn-based, Bi—In-based and the like Pb-free solders has amelting point of 260° C. or lower. Accordingly, when any one of theabove-described Pb-free solders is used alone for the connection, thesolder remelts in the case of reflow soldering, whereby the connectioncannot be maintained due to solder flash and exfoliation in theconnection interface.

Hence, it is necessary for making the melting point after the connectionto have a high melting point of 260° C. or higher as a result of theformation of a metal compound through the reaction of such a metal ofCu, Ag, Ni, or Au which reacts with any of the Sn, In, Sn—Ag-based,Sn—Cu-based, Sn—Ag—Cu-based, Sn—Zn-based, Sn—Zn—Bi-based, Sn—In-based,In—Ag-based, In—Cu-based, Bi—Sn-based, Bi—In-based and the like Pb-freesolders.

In this case, a thickness of the intermetallic compound layer in theconnection part is preferably 1 to 30 μm. When it is less than 1 μm,there may be a case where wettability cannot be assured over the wholeregion of the connection interface at the time of the connection,whereby poor connection arises. On the other hand, when the thickness ismore than 30 μm, there may be a case where a long period of time isrequired for achieving the complete compound of the connection part sothat the productivity is lowered. Besides, since the connection ispossible to be made at a temperature of 260° C. or lower, the residualstress appearing at the time of cooling after the die-mount-connectioncan be reduced.

As a result of providing a temperature stratum in the connection layeron the front and rear surfaces of the composite foil, when the compositefoil is supplied to the lead frame at a temperature at which only theconnection layer formed on the lead frame side of the stress bufferinglayer and a pressurizing step as well as a scrubbing step are appliedfrom the side of the unmelted connection layer formed on thesemiconductor element side of the stress buffering layer, theconnectability and the void evacuatability can be improved in theconnection part for the composite foil and lead frame. In addition, whenthe pressurizing and scrubbing steps are applied in the case ofsupplying the semiconductor element, the connectability and the voidevacuatability can be improved also in the connection part for thesemiconductor element and composite foil. In this case, it is desiredthat the lead frame is connected with the composite foil by means of acompound even which is locally formed in the connection layer formed onthe lead frame side of the stress buffering layer.

A present seventh invention provides a semiconductor device wherein asemiconductor element is die-mount-connected onto a lead frame by meansof a metal joint, characterized in that the metal joint contains anunreacted high melting point metal which does not react in the case ofthe die-mount-connection; and an intermetallic compound formed by thereaction in the case of joining the high melting point metal to thesemiconductor element as well as joining the high melting point metal tothe lead frame.

The above-described constitution may be effectively applied to the casewhere such chip cracks appearing at a high possibility of, for example,6/20 or the like in a conventional metal joint wherein there is athermal expansion coefficient difference of, for example, 5 ppm/° C. orhigher between the semiconductor element and the lead frame which hasbeen proposed heretofore and such chip cracks of which could not havebeen eliminated.

As mentioned above in the description of the present first invention,the chip cracks appeared on the semiconductor element side in thedie-mount joint section is due to such fact that since a thermalexpansion coefficient difference between the lead frame and thesemiconductor element to be joined is large, the semiconductor elementside cannot expand and contract in response to that of the lead frameside having a high thermal expansion coefficient. It may be consideredin this respect to be possible to suppress such chip crack by increasinga thickness of the metal joint section. In this connection, however,there arises such a problem that an Au-20Sn solder is expensive in thecase of the connection with a single material, while sufficient heatdissipation cannot be made by a Bi-based solder because the thermalexpansion coefficient thereof is 9 W/m·K being as low as about ⅓ of ahigh Pb solder. On the other hand, when the metal joint section is madeto be a complete compound, the joint section becomes rigid and brittle,besides considerable time is required for achieving the completecompound, whereby it is pointed out to involve such a problem that thetechnology mentioned herein is industrially inappropriate.

Accordingly, when the stress buffering layer is provided as mentionedabove, the metal joint section may be thickened with the stressbuffering layer and the connection layer itself may be thinned. As aresult, an amount of the Au-20Sn to be applied can be reduced, resultingin heat dissipation with the Bi-based solder having a low thermalexpansion coefficient, so that an amount of a rigid and brittleintermetallic compound may be reduced. Thus, it becomes possible toappear no chip crack within a range wherein a difference of coefficientsof thermal expansion extends from a small difference of, for example,about 4 ppm/° C. as in the case of Si and a ceramic substrate to a largedifference of about 14 ppm/° C. as in the case of Si and Cu as a resultof providing the stress buffering layer.

Under the circumstances, the present inventors considered to utilize ahigh melting point metal used for an intermetallic compound in theconstitution of the stress buffering layer. Heretofore, suchconstitution has not been practically applied, because there wasappearance of chip cracks in the thermal cycle tests after theconnection due to the rigid and brittle natures of the intermetalliccompound in the case where the whole metal joint for connecting thesemiconductor element with the lead frame wherein a thermal expansioncoefficient difference is 5 ppm/° C. or more is made from anintermetallic compound formed by the reaction with a high melting pointmetal in the case of joining the semiconductor element to the leadframe.

As in the present invention, however, either such an arrangement that aremaining part in an unreacted state is prepared purposely in the highmelting point metal used in the case of forming the intermetalliccompound, or such an arrangement that a high melting point metal layerwhich does not react with the intermetallic compound is separatelyprovided was previously prepared. As a result, such unreacted part ofthe high melting point metal as described above may function as a stressbuffering layer, so that such stress derived from the rigid and brittlenature of intermetallic compound and which leads appearance of chipcracks which could not have been avoided in the intermetallic compoundcomes to be possible to avoid by the stress buffering layer involvingsuch unreacted high melting point metal.

In also the experiments, it is confirmed that when a layer of suchunreacted high melting point metal is provided in the case of joining asemiconductor element to a lead frame wherein there is a thermalexpansion coefficient difference of 5 ppm/° C. between the semiconductorelement and the lead frame, the constitution of the intermetalliccompound can be applied. In the layer of such unreacted high meltingpoint metal, either of the metals used in the case of forming theintermetallic compound concerned with the joint structure of the actualsemiconductor element and the lead frame, or the metals, which are notconcerned with the formation of such intermetallic compound, may beapplied.

According to the constitution as mentioned above, when a temperaturecycle test of 500 cycles of −55° C.(30 min.)/150° C.(30 min.) wasimplemented with respect to twenty packages prepared by joining thesemiconductor element to the lead frame, it became possible that no chipcrack appeared in all cases.

It is very important to provide an unreacted metal layer having a highmelting point which does not react in a joint condition at the time ofdie-mount-connection in the metal joint section without constituting themetal joint by means of the complete compound. Even in the prior artdocuments 1 and 2 wherein there is an idea of joint in the intermetalliccompound, neither any description nor a suggestion, inclusive, is notfound with respect to such an unreacted high melting point metal layer.Accordingly, this is the unique conception involved in the inventionitself of the present application.

A present eighth invention provides a semiconductor device having asemiconductor element, and a substrate connected to the semiconductorelement, characterized in that the semiconductor element is connectedwith the substrate through a metal containing layer containing a metaland an intermetallic compound layer being thinner than the metalcontaining layer and including the metal component contained in themetal containing layer; and the connection between the semiconductorelement and the substrate does not melt even at the upper temperaturelimit of the semiconductor device.

A present ninth invention provides a semiconductor device having asemiconductor element, and a lead frame connected to the semiconductorelement through a connection part, characterized in that the connectionpart has a metal containing layer containing a metal and anintermetallic compound layer being thinner than the metal containinglayer and including the metal component contained in the metalcontaining layer; and the connection part does not melt even at theheat-resistant upper limit of the semiconductor device.

As shown in the above-described constitution, the semiconductor elementsuch as a semiconductor chip is connected with a substrate such as thelead frame through the metal containing layer and the intermetalliccompound having a metal component contained in the metal containinglayer in the present eighth and ninth inventions. Accordingly, a layerthickness of the intermetallic compound may be decreased as comparedwith a case where such a connection part is constituted by a singlelayer made of only intermetallic compound.

An intermetallic compound has a nature of a high allowable temperaturelimit, but it is rigid and brittle. And so when the intermetalliccompound is used for the connection of the semiconductor element with asubstrate as a single layer, to avoid effects such as appearance of thethermal stress produced in temperature cycles when it is used on theside of a semiconductor element, the thickness of the layer is made tobe thick to expect its buffering action in the thickness direction.

In the above-described present invention, however, since a layer of theintermetallic compound is applied as a multiple layer including a metalcontaining layer, it is possible to design an intermetallic compoundlayer thin unlike the case where the intermetallic compound is appliedas a single layer. Accordingly, when the metal containing layer isallowed to take on stress buffering function, it becomes unnecessarythat the intermetallic compound layer does not take on such stressbuffering function exclusively, whereby the intermetallic compound layermay be thinner than that of the metal containing layer. Thus, it becomespossible to assure the connection between the semiconductor element andthe substrate while buffering the thermal stress due to the fact thatthe semiconductor element side cannot expand and contract in response tothe expanding and contraction in the substrate side including the leadframe and the like having a large thermal expansion coefficient evenwhen there is a large thermal expansion coefficient difference betweenthe substrate such as the lead frame and the semiconductor element suchas a semiconductor chip. In other word, for example, the intermetalliclayer bends easily to follow the distortion as much as the intermetalliccompound layer may be thinned, so that it is advantageous from theviewpoint of buffering thermal stress as compared with the case wherethe layer thickness is thick.

When a layer thickness of such intermetallic compound layer isconsidered from a relationship of a connection area of the semiconductorelement and the substrate, it is required to apply the intermetalliccompound with a thickened connection part in the case where both theconnection areas of the semiconductor element and the substrate to beconnected are the same with each other, if the semiconductor element isconnected with the substrate by means of a single layer of theintermetallic compound, since the intermetallic compound has a highallowable temperature limit but is rigid and brittle as described above.In the present invention, however, since the intermetallic compound maybe constituted in the form of a multiple layer including a metalcontaining layer by which stress buffering function is taken on asdescribed above, a layer thickness thereof may be decreased within arange wherein connection reliability can be assured. Furthermore, thethinner layer thickness results in the less effects of stress.

A present tenth invention provides a semiconductor device wherein asemiconductor element is die-mount-connected onto a lead frame, then,the resulting product is subjected to wire-bonding, and resin-molding,characterized in that the die-mount-connected part is successivelyconsist of, from the semiconductor element side, an intermetalliccompound layer having a melting point of 260° C. or higher, a metalliccompound layer having a melting point of 260° C. or higher, and anotherintermetallic compound layer having a melting point of 260° C. or higherin this order.

The highest temperature is 260° C. in the case of reflow soldering of asemiconductor package onto a substrate, so that it is required that amelting point of the connection part is 260° C. or higher after theconnection in order to maintain the connection at the time of the reflowsoldering.

An intermetallic compound layer having a melting point of 260° C. orhigher is formed, for example, in the reaction of a solder having amelting point of 260° C. or lower with a metal having a melting point of260° C. or higher. In the case of the connection, the wettability isassured by the solder having a melting point of 260° C. or lower. At thesame time, the solder having a melting point of 260° C. or lower isallowed to react with the metal having a melting point of 260° C. orhigher, whereby an intermetallic compound is formed to make theconnection part to have a high melting point. In this case, since it ispossible to conduct the connection at a temperature of 260° C. or lower,it becomes possible to reduce the residual stress appeared in the caseof cooling after the die-mount-connection.

The metal layer having a melting point of 260° C. or higher is used forbuffering thermal stress. In the case where the connection part afterthe connection is only made from the intermetallic compound, theconnection part becomes rigid and brittle, so that the connectionreliability is remarkably damaged by chip cracks and cracks progressrapidly in the intermetallic compound. Hence, a metal layer, which canbuffer a stress, is provided in the connection part, whereby the thermalstress produced in the case of temperature cycles and cooling after theconnection is buffered to suppress the appearance of cracks therebyassuring the reliability.

Thus, the connection reliability can be assured in both cases of theconnection with a large thermal expansion coefficient difference betweena semiconductor element and a Cu-based lead frame and the connectionwith a small thermal expansion coefficient difference between thesemiconductor element and a 42-alloy lead frame.

A present eleventh invention provides the semiconductor device asdescribed in the tenth invention, characterized in that theintermetallic compound layer is formed by the reaction of at least oneof Sn—Ag-based, Sn—Cu-based, Sn—Ag—Cu-based, Sn—Zn-based,Sn—Zn—Bi-based, Sn—In-based, In—Ag-based, In—Cu-based, Bi—Sn-based, andBi—In-based Pb-free solders with at least one metal of Cu, Ag, Ni, andAu in the case of the die-mount-connection.

In the case of die-mount-connection, when the connection is executed ata temperature of 400° C. or higher, a Cu-based frame is softened, andhence, it is required to execute the connection at a temperature of 400°C. or lower. The Sn—Ag-based, Sn—Cu-based, Sn—Ag—Cu-based, Sn—Zn-based,Sn—Zn—Bi-based, Sn—In-based, In—Ag-based, In—Cu-based, Bi—Sn-based, andBi—In-based Pb-free solders have a melting point of 260° C. or lower.Accordingly, when they are applied alone for the connection, the solderis remelted in the case of reflow soldering, and accordingly, theconnection cannot be maintained due to appearance of solder flash andexfoliation in the connection interface.

Under the circumstances, it is necessary to make the melting point afterthe connection high, to have a melting point of 260° C. or higherthrough the reaction wherein a metal such as Cu, Ag, Ni, or Au whichreacts with the Sn—Ag-based, Sn—Cu-based, Sn—Ag—Cu-based, Sn—Zn-based,Sn—Zn—Bi-based, Sn—In-based, In—Ag-based, In—Cu-based, Bi—Sn-based, andBi—In-based Pb-free solders to form a metal compound. In this case, athickness of the intermetallic compound layer in the connection part ispreferably 1 to 30 μm. When it is less than 1 μm, the wettability overthe whole region of the connection interface at the time of connectioncannot be assured, so that there is a case where poor connectionappears. On the other hand, when the thickness is more than 30 μm, along period of time is required for achieving the complete compound ofthe connection part, so that there is a case where the productivitythereof becomes poor. In addition, since it is possible to make theconnection at a temperature of 260° C. or lower, it is possible toreduce a residual stress at the time of cooling after thedie-mount-connection.

A present twelfth invention provides a semiconductor device wherein asemiconductor element is die-mount-connected onto a lead frame, then,the resulting product is subjected to wire-bonding, and resin-molding,characterized in that the die-mount-connected part is successivelyconsist of, from the semiconductor element side, a Pb-free solder layerhaving a melting point of 260° C. or higher to 400° C. or lower, ametallic compound layer having a melting point of 260° C. or higher, andanother Pb-free solder layer having a melting point of 260° C. or higherto 400° C. or lower, in this order.

The connection is made by using a Pb-free solder having a melting pointof 260° C. or higher to 400° C. or lower. The reason for making thesolder to have a melting point of 260° C. or higher is in that thesolder is not remelted in the case of reflow soldering. On the otherhand, the reason for making the solder to have a melting point of 400°C. or lower is in that there is such a problem that when thedie-mount-connection is conducted at a temperature of 400° C. or higher,the Cu-based frame becomes softened to be deformed.

The reason for providing a metal layer having a melting point of 260° C.or higher is in that the thermal stress produced by temperature cyclesand cooling after the connection is to be buffered thereby suppressingappearance of chip cracks. As a result of providing the metal layer, theconnection reliability can be assured in both cases of the connectionwith a large thermal expansion coefficient difference between asemiconductor element and a Cu-based lead frame and the connection witha small thermal expansion coefficient difference between thesemiconductor element and a 42-alloy lead frame.

A present thirteenth invention provides the semiconductor device asdescribed in the twelfth invention, characterized in that the Pb-freesolder layer having a melting point of 260° C. or higher to 400° C. orlower is made of at least any one of Au—Sn-based alloy, Au—Ge-basedalloy, Au—Si-based alloy, Zn—Al-based alloy, Zn—Al—Ge-based alloy, Bi,Bi—Ag-based alloy, Bi—Cu-based alloy, and Bi—Ag—Cu-based alloy.

The reason why a Pb-free solder having a melting point of 260° C. orhigher to 400° C. or lower is used is in that when a melting point ofthe solder is 260° C. or lower, there is such a problem that the solderis remelted in the case of reflow soldering, while when the meltingpoint is 400° C. or higher, there is such a problem that a Cu-basedframe becomes softened at the time of the die-mount-connection,resulting in deformation.

Since it is possible to buffer thermal stress by means of a metal layer,the reliability can be assured even in the case where theabove-described Pb-free solder is thinned. As a result, usage of thesolder may be reduced even in the case of using an expensive Au-basedsolder. In this case, a thickness in the connection of such solder ispreferably 1 μm or more. When it is less than 1 μm, the wettability inthe whole region of the connection interface cannot be assured in thecase of the connection, whereby resulting in poor connection.

A present fourteenth invention provides the semiconductor device asdescribed in the tenth to thirteenth inventions, characterized in thatthe metal layer having a melting point of 260° C. or higher is made ofany one of Al, Mg, Ag, Zn, Cu, and Ni.

Al, Mg, Ag, Zn, Cu, and Ni has a smaller yield stress than that of anAu-20Sn which is a hard solder, so that it is easily subjected toplastic deformation. In this respect, thermal stress is buffered as aresult of plastic deformation of Al, Mg, Ag, Zn, Cu, or Ni. In thiscase, it is desired that a magnitude of yield stress of the metal layeris 75 MPa or less as shown in FIG. 3. When the yield stress is 100 MPaor more, the thermal stress cannot sufficiently be buffered, so that thestress appeared in a semiconductor element becomes large, whereby thereis a case where chip cracks appear. Although it does not mainly dependon the Young's modulus of a material to be used, but the smaller valueis the more preferred. Moreover, a thickness thereof is preferably 30 to200 μm. When the thickness is less than 30 μm, the thermal stress cannotbe sufficiently buffered, so that there is a case where chip cracksappear. On the other hand, when the thickness is 200 μm or more, theeffect of thermal expansion coefficient increases, because Al, Mg, Ag,or Zn has a larger thermal expansion coefficient than that of theCu-frame, and as a result, there is a case of leading decrease inreliability with respect to appearance of chip cracks and the like.

A present fifteenth invention provides the semiconductor device asdescribed in the tenth to thirteenth inventions, characterized in thatthe metal layer having a melting point of 260° C. or higher is made ofat least one of Cu/Invar alloy/Cu composite material, Cu/Cu₂O compositematerial, Cu—Mo alloy, Ti, Mo, and W.

The Cu/Invar alloy/Cu composite material, Cu/Cu₂O composite material,Cu—Mo alloy, Ti, Mo, or W has a thermal expansion coefficient rangingfrom that of the semiconductor element to that of the Cu-based leadframe, whereby the thermal stress is buffered. In this case, a thicknessthereof is preferably 30 μm or more. When the thickness is less than 30μm, the thermal stress cannot be sufficiently buffered, so that there isa case where chip cracks appear.

A present sixteenth invention provides a manufacturing method for asemiconductor device wherein a semiconductor element isdie-mount-connected onto a lead frame by means of a metal joint, whereinthe metal joint is formed by heating a composite foil in a conditionwhere the composite foil comprising a layer composing a metal having amelting point of 260° C. or lower and a metal having a melting point of260° C. or higher that react to form an intermetallic compound having amelting point of 260° C. or less, the composite foil is disposed on thesemiconductor element side and the lead frame side of a metal layerhaving a melting point of 260° C. or higher, the semiconductor elementand the lead frame are interposing the composite foil between the metallayer.

A present seventeenth invention provides the manufacturing method for asemiconductor device as described in the sixteenth invention,characterized in that the metal layer having a melting point of 260° C.or higher is formed by any one of Al, Mg, Ag, Zn, Cu, and Ni; the metalhaving a melting point of 260° C. or lower and forming an intermetalliccompound having a melting point of 260° C. or higher as a result ofreaction is any one of Sn—Ag-based, Sn—Cu-based, Sn—Ag—Cu-based,Sn—Zn-based, Sn—Zn—Bi-based, Sn—In-based, In—Ag-based, In—Cu-based,Bi—Sn-based, and Bi—In-based Pb-free solders; and the metal having amelting point of 260° C. or higher and forming an intermetallic compoundhaving a melting point of 260° C. or higher as a result of reaction isany one metal of Cu, Ag, Ni, and Au.

According to the present invention, in the case of reflow soldering of amaterial onto a substrate at the highest temperature of 260° C., it ispossible to provide a Pb-free power semiconductor device withaccompanying no flash of the solder in a die-mount-connection part andalso a high connection reliability in the die-mount-connection part of apower semiconductor element and a lead frame in the power semiconductordevice under the actual use environment even in the case where a thermalexpansion coefficient difference is large between the materials to beconnected.

As described above, according to the present invention, it is possibleto conduct a Pb-free die-mount connection without causing any chip crackwith respect to thermal stress, and with no melting of the solder in thecase of reflowing.

BRIEF DESCRIPTIONS OF THE DRAWINGS

FIG. 1 is a sectional view schematically showing a configuration of aconventional power semiconductor device;

FIG. 2 is an explanatory view showing the appearance of flash due to aremelted solder;

FIG. 3 is a diagram showing Young's modulus and yield stresses of avariety of materials applicable for a stress buffering layer;

FIG. 4 is a sectional view schematically showing the power semiconductordevice regarding to the present embodiment;

FIG. 5A is a sectional view schematically showing the constitution of acomposite foil, and FIG. 5B is a sectional view schematically showingthe appearance of a metal joint;

FIG. 6 is a perspective view schematically showing the composition ofthe power semiconductor device used in the experiment for determining atemperature and a retention time required for achieving a completecompound of a connection layer;

FIGS. 7A, 7B and 7C are sectional photographs each showing a connectionsection wherein Si is connected to Cu by the use of Sn-3Ag-0.5Cu at 350°C. in which the holding time is 1 minute, 5 minutes, and 10 minutes,respectively;

FIG. 8 is a sectional view schematically showing a modified example ofthe composite foil;

FIG. 9 is an example of a sectional photograph showing a situation ofthe connection part after applying the temperature cycles of Example 11;

FIG. 10 is an example of a sectional photograph showing a situation ofthe connection part after applying the temperature cycles of Example 14;

FIG. 11A is a sectional view schematically showing a modified example ofthe power semiconductor device according to the present embodiment; andFIG. 11B is a plan view showing a connecting condition of a powersemiconductor element viewed from above;

FIG. 12 is an example of a sectional photograph showing appearance of achip crack;

FIG. 13A is a sectional view schematically showing appearance of amodified example of the metal joint; and FIG. 13B is a sectional viewschematically showing appearance and composition a modified example ofthe composite foil used for forming the metal joint shown in FIG. 13A;

FIGS. 14A through 14G are explanatory views each schematicallyillustrating a procedure in the case of manufacturing the semiconductordevice die-mount-connected by means of the metal joint wherein thecomposite foil is used;

FIG. 15A is a sectional view schematically showing appearance of amodified example of the metal joint; and FIG. 15B is a sectional viewschematically showing appearance and composition of a modified exampleof the composite foil used for forming the metal joint shown in FIG.15A; and

FIG. 16A is a sectional view showing schematically the appearance of amodified example of a metal joint; and FIG. 16B is a sectional viewschematically showing a modified example of the composite foil used forforming the metal joint shown in FIG. 16A.

BEST MODE FOR CARRYING OUT THE INVENTION

In the following, embodiments of the present invention will be describedby referring to the accompanying drawings.

Embodiment 1

FIG. 4 is a sectional view showing a semiconductor device 8 according toan embodiment of the present invention wherein the semiconductor device8 comprising a power semiconductor device 8 a and the like ismanufactured in accordance with, for example, the followingmanufacturing processes.

That is, as shown in FIG. 4, the power semiconductor device 8 a isobtained by die-mount-connecting a semiconductor element 1 as a powersemiconductor element 1 a onto a lead frame 2 through a metal jointsection 7. To form the metal joint section 7, a composite foil 7 a forforming the joint section shown in FIG. 5A is disposed on a die pad ofthe lead frame 2, and further the power semiconductor device 8 a isdisposed on the composite foil 7 a and heated.

For instance, on the rear surface on the silicon (Si) side of the powersemiconductor element 1 a being in contact with the composite foil 7 a,Ti/Ni/Au is metallized to assure the wettability. The lead frame 2 is,for example, made of a copper(Cu)-based material having good coefficientof thermal conductivity. The power semiconductor element 1 a and thelead frame 2 having such composition as described above are joined tothe metal joint section 7 formed by such a manner that the compositefoil 7 a interposed between the power semiconductor element 1 a and thelead frame 2 is heated at a predetermined temperature to melt andsolidify at the time of die-mount-connecting.

The composite foil 7 a for forming the metal joint section 7 is made of,for example, a metal layer 100 having a high melting point of 260° C. orhigher sandwiched between other metal layers 110 each having a highmelting point of 260° C. or higher, and further the other metal layers120 laminated on the metal layers 110 having a low melting point of 260°C. or lower. In order to assure the wettability between the powersemiconductor element 1 a or the lead frame 2, the metal layer 120 of alow melting point metal is disposed on the metal layer 110 of a highmelting point metal.

Examples of the metals to constitute the metal layer 100 includealuminum (Al), magnesium (Mg), silver (Ag), zinc (Zn), copper (Cu),nickel (Ni), and the like. Since such metal has a smaller yield stressthan that of Au-20Sn as a hard solder, it is easily subjected to plasticdeformation. Thus, when a thermal stress appears in the metal jointsection 7, the metal layer 100 is subjected to plastic deformation,whereby the stress reaches to the side of the power semiconductor device8 a, so that the metal layer 100 brings out a function for buffering thethermal stress so as not to result in a damage such as occurrence ofcracks.

As shown in FIG. 3, from the present experimental results by the presentinventors, it was found that, when the yield stress of the metal layer100 is 100 MPa or more, the thermal stress cannot be sufficientlybuffered, whereby the stress produced on the semiconductor elementincreases, so that there is a case where chip cracks occur. Accordingly,it is preferred that the yield stress is less than 100 MPa, and morepreferably a magnitude of the yield stress is 75 MPa or less as shown inFIG. 3.

Concerning a stress buffering function of the metal layer 100, althoughit does not significantly depend on Young's modulus of a materialconstituting the metal layer 100, the smaller value is the morepreferable.

A thickness of the metal layer 100 is preferably to be 30 to 200 μm.When the thickness is less than 30 μm, the thermal stress is notsufficiently buffered, so that there is a case where chip cracks appear.On the other hand, when the thickness is 200 μm or more, effects ofthermal expansion coefficient increase because of Al, Mg, Ag, or Znhaving a larger thermal expansion coefficient than that of the Cu frame.Hence, there is a case where it results in decrease in reliability dueto the generation of chip cracks and the like.

On the other hand, examples of the high melting point metal toconstitute the metal layer 110 include copper (Cu), silver (Ag), nickel(Ni), gold (Au) and the like. Furthermore, as a low melting point metalconstituting the metal layer 120, any of Sn—Ag-based (tin-silver-based),Sn—Cu-based (tin-copper-based), Sn—Ag—Cu-based(tin-silver-copper-based), Sn—Zn-based (tin-zinc-based), Sn—Zn—Bi-based(tin-zinc-bismuth-based), Sn—In-based (tin-indium-based), In—Ag-based(indium-silver-based), In—Cu-based (indium-copper-based), Bi—Sn-based(bismuth-tin-based), and Bi—In (bismuth-indium-based) Pb-free solders ispreferably applied.

The metal layers 110 may be provided on the metal layer 110 by means of,for example, sputtering or plating technique. Similarly, the metallayers 120 may be also provided on the metal layers 110, respectively,by means of, for example, sputtering or plating technique.

In the composite foil 7 a having such configuration as described above,the high melting point metal constituting the metal layers 110 and thelow melting point metal constituting the metal layers 120 are melted toreact with each other as a result of heating at the time ofdie-mount-connection, whereby both connection layers 200 are formed onthe metal layer 100 as shown in FIG. 5B.

The connection layer 200 is a product formed by the reaction of the highmelting point metal of the metal layer 110 with the low melting pointmetal of the metal layer 120. Judging from the microgram of a section ofthe metal joint section 7, the product exhibits a condition wherein aplurality of phases of: an intermetallic compound of such a low meltingpoint metal and a high melting point metal; another intermetalliccompound of the low melting point metal, the high melting point metal,and a metal metallized on the rear surface of the semiconductor element1; and a single phase metal and the like exist being mixed in the meltedmetal phase of a low melting point metal.

When the connection layer 200 formed by the reaction of a high meltingpoint metal constituting the metal layer 110 with a low melting pointmetal constituting the metal layer 120 is held, for example, at 350° C.for 10 minutes after the die mounting, the connection layer 200 turns tohave a high melting point as a result of achieving a complete compoundthrough the reaction of a metal having a melting point of 260° C. orlower with another metal having a melting point of 260° C. or higher.

In the power semiconductor element 1 a die-mount-connected by means ofthe metal joint section 7 which was modified to have a high meltingpoint, the electrode formed on the top of the power semiconductorelement 1 a is then bonded to the leads 5 by using the Au wires 4,respectively. In addition, the power semiconductor element 1 a, the leadframe 2, the metal joint section 7, and the wires 4 are sealed with theuse of an epoxy-based resin 6. According to the above-describedprocesses, the power semiconductor device 8 a is manufactured.

Such a condition that the composite foil 7 a sandwiched between thepower semiconductor element 1 a and the lead frame 2 is held at 350° C.for 10 minutes in the case of achieving a complete compound of theconnection layer 200 formed by the reaction of the metal layer 110 withthe metal layer 120 is determined by the experimental results whereinconnection temperatures and holding times are applied as the parametersin a variety of connection structures shown in Table 1.

Namely, the experiments were conducted in such a manner that a compositefoil 7 b which becomes the connection layer 200 having a high meltingpoint as a result of heating the composite foil 7 b is interposedbetween the 5 mm square power semiconductor element 1 a and the Cu leadframe 2 to which no mold was applied as shown schematically in FIG. 6.

An example of the composite foil 7 b applied includes, as shown in Table1, an Sn composite foil of 20 μm layer thickness, an Sn-3Ag-0.5Cucomposite foil of 20 μm layer thickness, an Sn-9Zn composite foil of 20μm, an In-48Sn composite foil of 20 μm layer thickness, and an Sn-0.7Cucomposite foil of 20 μm layer thickness. Each of the composite foils 7 bis interposed between the power semiconductor element 1 a and the leadframe 2, and it is heated at each of temperatures of 300° C., 350° C.,and 400° C. for each of holding times 1 minute, 3 minutes, 5 minutes, 10minutes, 30 minutes, and 60 minutes, respectively. Then, each conditionof the achievement of complete compounds was confirmed with respect ofeach of the connection layers 200 after the heating.

Note that, the composite foil 7 b does not contain the constitutioncorresponding to the metal layer 100 exerting the above-mentioned stressbuffering functions, because the experiments are conducted for thepurposes of determining the heating temperatures and the heating holdingtime required for achieving the complete compounds forming theconnection layer 200.

TABLE 1 Connection Holding Time Connection Structure Temperature 1 min.3 min. 5 min. 10 min. 30 min. 60 min. Si/Sn(20 μm)/Cu 300° C. X X X X603 603 350° C. X X X 603 603 603 400° C. X X X 603 603 603Si/Sn—3Ag—0.5Cu(20 μm)/Cu 300° C. X X X X 603 603 350° C. X X X 603 603603 400° C. X X X 603 603 603 Si/Sn—9Zn(20 μm)/Cu 300° C. X X X 603 603603 350° C. X X X 603 603 603 400° C. X X X 603 603 603 Si/In—48Sn(20mm)/Cu 300° C. X X X 603 603 603 350° C. X X X 603 603 603 400° C. X X X603 603 603 Si/Sn—0.7Cu(20 mm)/Cu 300° C. X X X 603 603 603 350° C. X XX 603 603 603 400° C. X X X 603 603 603

Table 1 was obtained by sorting out the results with respect to theachievement of the complete compounds of the connection parts of thesamples to which Si/solder/Cu connection was applied. As shown in Table1, it was found that the complete compounds of the connection layers 200can be achieved in the case where the heating temperature is 350° C. orhigher and the holding time is 10 minutes or more as a result of theexperiments wherein the composite foils 7 b having the above-describedfive types of constitutions are applied.

Incidentally, FIGS. 7A to 7C indicate each of conditions of theconnection sections wherein a semiconductor element (Si) is connectedwith Cu at 350° C. by using Sn-3Ag-0.5Cu solder. FIGS. 7A and 7B arephotographs of sectional views in the case where the holding time is 1minute and 5 minutes, respectively, wherein it is found that Sn having amelting point of 260° C. or lower remains. In the case where the Sn,which does not reach the complete compound remains, remelting of asolder constituting the connection layer 200 arises at the time ofreflow soldering. On the other hand, it is confirmed as shown in FIG. 7Cthat when the holding time is 10 minutes, the connection layer 200 iscompletely turned into a whole compound with Cu—Sn and an Ag—Sncompound.

Next, effectiveness of the present invention was verified in the casewhere the power semiconductor element 1 a was die-mount-connected byusing the composite foil 7 a to which the metal layer 100 exertingstress buffering functions as shown in FIG. 5A was applied, and thethermal stress due to temperature cycles was applied repeatedly.

More specifically, the experiments were conducted in such a manner thatthe composite foil 7 a obtained by laminating the metal layers 110 and120 on the metal layer 100 which becomes the connection layer 200 havinga high melting point as a result of heating them is interposed betweenthe 5 mm square power semiconductor element 1 a and the Cu lead frame 2to which no mold has been applied.

The composite foil 7 a to be used is prepared in example 1, as shown intable 2, in such that the metal layer 100 is made of an Al layer havinga layer thickness of 100 μm, the metal layer 110 is made of Cu, themetal layer 120 is made of Sn, and a layer thickness of a combination ofthose of the metal layers 110 and 120 is made to be 10 μm.

A layer thickness of the metal layers 110 and 120 may be determined, forexample, to be the layer thickness corresponding to such an amountwherein a metal of a low melting point does not remain in the form ofthe single phase thereof in the case where a metal having a high meltingpoint constituting the metal layer 110 reacts with the metal having alow melting point constituting the metal layer 120 to form anintermetallic compound as described later. This is because the metal ofa low melting point remelts at the temperature of 260° C. in the case ofreflow in a condition wherein a metallic phase of the low melting pointremains, whereby there is a fear of a cause for occurring flash.

A semiconductor package is formed by using the power semiconductordevice 8 a having the constitution shown in FIG. 4 which is obtained asa result of the die-mount-connection wherein the composite foil 7 ahaving the above-described constitution is interposed between the powersemiconductor element 1 a and the Cu-based lead frame 2, and they aremaintained at a heating temperature of 350° C. for a holding time of 10minutes while keeping the interposed condition.

With respect to twenty power semiconductor packages each having theabove-described constitution, a temperature cycle test for 500 cycles of−55° C.(30 min.)/150° C.(30 min.) was implemented. The temperature cycletest was conducted by setting the semiconductor package in athermal-shock tester. When the connection section after the temperaturecycle test is observed, in the case where the metal layer 100 of Al inexample 1 functions to buffer thermal stress, cracks appear in an arearatio of Al of less than 5% wherein the area extending from the end ofAl to the connection section, while no chip crack appears in the side ofthe power semiconductor element 1 a.

TABLE 2 Package Chip No. Structure Frame Configuration ofDie-Mount-Connection Crack Example 1 FIG. 4 Cu-Based Cu + Sn/Al/Cu + Sn= 10 μm/100 μm/10 μm 0/20 2 FIG. 4 Cu-Based Cu + Sn—3Ag—0.5Cu/Al/Cu +Sn—3Ag—0.5Cu = 10 μm/100 μm/10 μm 0/20 3 FIG. 4 Cu-Based Cu +Sn—9Zn/Al/Cu + Sn—9Zn = 10 μm/100 μm/10 μm 0/20 4 FIG. 4 Cu-Based Au +Sn/Al/Au + Sn = 10 μm/100 μm/10 μm 0/20 5 FIG. 4 Cu-Based Ni +Sn/Al/Ni + Sn = 10 μm/100 μm/10 μm 0/20 6 FIG. 4 Cu-Based Ag +Sn/Al/Ag + Sn = 10 μm/100 μm/10 μm 0/20 7 FIG. 4 Cu-Based Cu +In—48Sn/Al/Cu + In—48Sn = 10 mμm/100 μm/10 μm 0/20 8 FIG. 4 Cu-BasedAg + Bi—43Sn/Al/Ag + Bi—43Sn = 10 mμm/100 μm/10 μm 0/20 9 FIG. 4Cu-Based Cu + Sn/Zn/Cu + Sn = 10 μm/100 μm/10 μm 0/20 10 FIG. 4 Cu-BasedSn/(Cu/Inver/Cu)/Sn = 10 μm/100 μm/10 μm 0/20 11 FIG. 4 Cu-BasedAu—20Sn/Al/Au—20Sn = 20 μm/100 μm/20 μm 0/20 12 FIG. 4 Cu-BasedAu—20Sn/Zn/Au—20Sn = 20 μm/100 μm/20 μm 0/20 13 FIG. 4 Cu-BasedZn—6Al/Al/Zn—6Al = 20 μm/100 μm/20 μm 0/20 14 FIG. 4 Cu-BasedAu—20Sn/(Cu/Inver/Cu)/Au—20Sn = 20 μm/100 μm/20 μm 0/20 15 FIG. 4Cu-Based Au—20Sn/Ti/Au—20Sn = 20 μm/100 μm/20 μm 0/20 16 FIG. 4 Cu-BasedBi—Ag/Al/Bi—Ag = 20 μm/100 μm/20 μm 0/20 17 FIG. 4 Cu-BasedBi/(Cu/Inver/Cu)/Bi = 20 μm/100 μm/20 μm 0/20 18 FIG. 11 Cu-Based Cu +Sn/Al/Cu + Sn = 10 μm/100 μm/10 μm 0/20 19 FIG. 4 42-Alloy Cu +Sn/Al/Cu + Sn = 10 μm/100 μm/10 μm 0/20 20 FIG. 4 Cu-Based Au—20Sn/Al/Bi= 20 μm/100 μm/20 μm 0/20 21 FIG. 4 Cu-Based Au—20Sn/(Cu/Inver/Cu)/Bi =20 μm/100 μm/20 μm 0/20 22 FIG. 4 Cu-Based Au—20Sn/Al/Bi—3Ag = 20 μm/100μm/20 μm 0/20 23 FIG. 4 Cu-Based Zn—9Al/Al/Au—20Sn = 20 μm/100 μm/20 μm0/20 24 FIG. 4 Cu-Based Au—20Sn/(Cu/Inver/Cu)/Sn = 10 μm/100 μm/10 μm0/20 25 FIG. 4 Cu-Based Bi/(Cu/Inver/Cu)/Sn = 10 μm/100 μm/10 μm 0/20 26FIG. 4 Cu-Based Cu + Sn/Al/Cu + In—48Sn = 10 μm/100 μm/10 μm 0/20 27FIG. 4 Cu-Based Ag + Sn/Al/Ag + Sn—9Zn = 20 μm/100 μm/20 μm 0/20 28 FIG.4 Cu-Based Sn/(Cu/Inver/Cu)/In—48Sn = 10 μm/100 μm/10 μm 0/20 29 FIG. 4Cu-Based Sn—3.5Ag/(Cu/Inver/Cu)/In—48Sn = 10 μm/100 μm/10 μm 0/20 30FIG. 4 Cu-Based Sn/(Cu/Inver/Cu)/Sn—9Zn = 10 μm/100 μm/10 μm 0/20 31FIG. 4 Cu-Based Cu + Au—20Sn/Al/Cu + Sn = 20 μm/100 μm/20 μm 0/20 32FIG. 4 Cu-Based Cu + Bi/Al/Cu + Sn = 10 μm/100 μm/10 μm 0/20 Comparative1 FIG. 4 Cu-Based Pb—5Sn = 20 μm 0/20 Example 2 FIG. 4 Cu-Based Cu + Sn= 20 μm 6/20 3 FIG. 4 Cu-Based Au—20Sn = 20 μm 5/20 Temperature CycleTest: 500 Cycles. Si/Composite Foil/Cu. 5 mm□. No Mold

Table 2 is obtained by sorting out results of the temperature cycle testwherein the samples prepared as a result of die-mount-connection by theuse of the composite foil 7 a applied in the present invention togetherwith the results of comparative examples. As shown in Table 2, no chipcrack appeared in all the twenty samples; and further no appearance ofcrack and the like were observed on the side of the power semiconductorelement 1 a in spite of the fact that repeated thermal stress due to thetemperature cycles was applied. Namely, it has been verified that theconnection reliability of the die-mount-connection by the use of thecomposite foil 7 a according to the present invention is effective inexample 1.

It is supposed that such effectiveness is due to the fact that thethermal stress derived from temperature cycle is buffered by the metallayer 100 of Al, so that such adverse effects of cracks on the side ofthe power semiconductor element 1 a due to the thermal stress did notappear. More specifically, the stress as to extraction and contractionof the Cu lead frame is absorbed by the metal layer 100 on which theconnection layer 200 is laminated in such large extraction andcontraction in the Cu lead frame 2 having a large thermal expansioncoefficient as to thermal stress.

Thus, the shear stress based on expansion and contraction on the side ofthe Cu lead frame 2 is absorbed as a result of the appearance of cracksin the metal layer 100, so that such a degree of the stress due to whichchip cracks appear on the power semiconductor element 1 a through theconnection layer 200 laminated on the metal layer 100 is not transmittedto the side of the power semiconductor element 1 a.

The same tendency could have been confirmed also in examples 2 through10 indicated in Table 2 wherein the same temperature cycle test isconducted. In example 2, the composite foil 7 a applied is made of, asindicated in Table 2, the metal layer 100 made of an Al layer having 100μm layer thickness, the metal layer 110 made of Cu, and the metal layer120 made of a Pb-free solder of Sn-3Ag-0.5Cu wherein the total layerthickness of the metal layers 110 and 120 is made to be 10 μm. In thiscase, although cracks appeared in an area ratio of Al constituting themetal layer 100 of less than 5% wherein the area extending from the endof Al to the connection section, no chip crack appeared in all thetwenty samples.

In example 3, the composite foil 7 a applied is made of, as indicated inTable 2, the metal layer 100 made of an Al layer having 100 μm layerthickness, the metal layer 110 made of Cu, and the metal layer 120 madeof a Pb-free solder of Sn-9Zn wherein the total layer thickness of themetal layers 110 and 120 is made to be 10 μm. In example 3 also,although cracks appeared in an area ratio of Al within a range of lessthan 5%, no chip crack appeared in all the twenty samples as in the caseof the above-described example 1.

In example 4, the composite foil 7 a applied is made of, as indicated inTable 2, the metal layer 100 made of an Al layer having 100 μm layerthickness, the metal layer 110 made of Au, and the metal layer 120 madeof Sn wherein the total layer thickness of the metal layer 110 and 120is made to be 10 μm. In example 4 having the above-describedconstitution also, although cracks appeared in an area ratio of Alwithin a range of less than 5%, no chip crack appeared in all the twentysamples as in the case of the above-described example 1.

In example 5, the composite foil 7 a applied is made of, as indicated inTable 2, the metal layer 100 made of an Al layer having 100 μm layerthickness, the metal layer 110 made of Ni, and the metal layer 120 madeof Sn wherein the total layer thickness of the metal layer 110 and 120is made to be 10 μm. In example 6, the composite foil 7 a applied ismade of, as indicated in Table 2, the metal layer 100 made of an Allayer having 100 μm layer thickness, the metal layer 110 made of Ag, andthe metal layer 120 made of Sn wherein the total layer thickness of themetal layers 110 and 120 is made to be 10 cm.

In example 7, the composite foil 7 a applied is made of, as indicated inTable 2, the metal layer 100 made of an Al layer having 100 μm layerthickness, the metal layer 110 made of Cu, and the metal layer 120 madeof In-48Sn wherein the total layer thickness of the metal layers 110 and120 is made to be 10 μm. In example 8, the composite foil 7 a applied ismade of, as indicated in Table 2, the metal layer 100 made of an Allayer having 100 μm layer thickness, the metal layer 110 made of Ag, andthe metal layer 120 made of Bi-43Sn wherein the total layer thickness ofthe metal layers 110 and 120 is made to be 10 μm.

In examples 5 to 8 having also the above-described constitutions,respectively, although cracks appeared in an area ratio of Al within arange of less than 5%, no chip crack appeared in all the twenty samplesas in the case of the above-described example 1.

In example 9, the composite foil 7 a applied is made of, as indicated inTable 2, the metal layer 100 made of an Zn layer having 100 μm layerthickness, the metal layer 110 made of Cu, and the metal layer 120 madeof Sn wherein the total layer thickness of the metal layers 110 and 120is made to be 10 μm. In example 10, the composite foil 7 a applied ismade of, as indicated in Table 2, the metal layer 100 made of a Cu/Invaralloy/Cu layer having 100 μm layer thickness, the metal layer 110 usingcommonly the Cu with that of the metal layer 100, and the metal layer120 made of Sn wherein the layer thickness of the metal layer 120 of Snis made to be 10 μm.

In the case of example 9, although cracks appeared in an area ratio ofZn constituting the metal layer 100 of less than 5% wherein the areaextending from the end of Zn to the connection section, no chip crackappeared in all the twenty samples. The case of example 10 is the onewherein the metal layer 100 is the Cu/Invar alloy/Cu having theintermediate thermal expansion coefficient in between Si and Cu; andwhen the connection section thereof is observed, there was no appearanceof cracks in any of the Si, the intermetallic compound, and the Cu/Invaralloy/Cu.

From the results of examples 1 through 10, it has been found that, theconstitutions of the present invention, thermal stress due to thetemperature cycles can be buffered by the metal layer 100 accompanied byAl, Zn, or the Cu/Invar alloy/Cu and further there is no appearance ofdrawbacks such as chip cracks, so that the constitutions of theinvention exhibit sufficient connection reliability.

According to the experiments by the present inventors, it has beenconfirmed that the formation of an intermetallic compound in theconnection layer 200 arises in the interface between a melted metal of alow melting point and another metal of a high melting point. Such acondition wherein the formed compound falls off from the interface intothe melted metal in the form of, for example, floating islands wasobserved. It seems that layers of compounds and the like having pluralcompositions are mixed in a metal of a low melting point to forminhomogeneous textures.

For instance, in the experiments of actual condition, it has beenconfirmed that Cu—Sn compounds (Cu₆Sn₅, Cu₃Sn), Cu—Ni—Sn compounds areformed on the chip side, while Cu—Sn compounds (Cu₆Sn₅, Cu₃Sn) areformed on the Cu frame side in the case where Sn is used as the metal ofa low melting point, and Cu is used as the metal of a high melting pointin examples 1, 9, and 10.

As the phases formed in example 2 (Cu+Sn-3Ag-0.5Cu), it has beenconfirmed that phases of Cu—Sn compounds (Cu₆Sn₅, Cu₃Sn), Ag—Sncompounds (Ag₃Sn), and Cu—Ni—Sn compounds are present on the chip side,while phases of Cu—Sn compounds (Cu₆Sn₅, Cu₃Sn), and Ag—Sn compounds(Ag₃Sn) are present on the Cu frame side.

As the phases formed in example 3 (Cu+Sn-9Zn), it has been confirmedthat phases of Cu—Sn compounds (Cu₆Sn₅, Cu₃Sn), and Cu—Zn compounds arepresent on the chip side, while phases of Cu—Zn compounds, and Cu—Sncompounds (Cu₆Sn₅, Cu₃Sn) are present on the Cu frame side.

As the phases formed in example 4 (Au+Sn), it has been confirmed thatphases of Au—Sn compounds are present on the chip side, while phases ofAu—Sn compounds, and Cu—Sn compounds (Cu₆Sn₅, Cu₃Sn) are present on theCu frame side.

As the phases formed in example 5 (Ni+Sn), it has been confirmed thatphases of Ni—Sn compounds are present on the chip side, while phases ofNi—Sn compounds, Cu—Sn compounds (Cu₆Sn₅, Cu₃Sn), and Ni—Cu—Sn compoundsare present on the Cu frame side.

As the phases formed in example 6 (Ag+Sn), it has been confirmed thosephases of Ag—Sn compounds (Ag₃Sn), and Ag-rich hcp phases are present onthe chip side, while phases of Ag—Sn compounds (Ag₃Sn), Ag-rich hcpphases, and Cu—Sn compounds (Cu₆Sn₅, Cu₃Sn) phases are present on the Cuframe side.

As the phases formed in example 7 (Cu+In-48Sn), it has been confirmedthat phases of Cu—Sn compounds (Cu₆Sn₅, Cu₃Sn), In—Cu compounds, andIn—Sn—Cu compounds are present on the chip side, while phases of Cu—Sncompounds (Cu₆Sn₅, Cu₃Sn), In—Cu compounds, and In—Sn—Cu compounds arepresent on the Cu frame side.

As the phases formed in example 8 (Ag+Bi-43Sn), it has been confirmedthat phases of Ag—Sn compounds (Ag₃Sn), Ag-rich hcp phases and, Biphases are present on the chip side, while phases of Ag—Sn compounds(Ag₃Sn), Ag-rich hcp phases, Bi, and Cu—Sn compound (Cu₆Sn₅, Cu₃Sn)phases are present on the Cu frame side.

Embodiment 2

As is apparent from the above-described embodiment 1, such aconstruction which is not adversely affected, e.g. with appearance ofcracks, by the rigid and brittle connection layer 200 and the side ofthe power semiconductor element 1 a connected with the connection layer200 may be obtained by the provision of the metal layer 100 whereinthermal stress is absorbed by the metal layer 100, even if theconnection layer 200 comes to have a high melting point resulting inrigid and brittle characteristics.

In this connection, the present inventors get such an idea that when aPb-free solder of a high melting point is used together with the metallayer 100, it becomes possible to use the Pb-free solder which could nothave been used for the die-mount-connection because of occurrence ofcracks by thermal stress on the chip side due to the rigid and brittlecharacteristics thereof although there is no fear of the remelting inthe case of the reflow by making it to have a high melting point.

More specifically, in the present embodiment, such a constitutionwherein Pb-free solder layers being metal layers 130 with which a highmelting point may be achieved are provided on the opposite surfaces of ametal layer 100 as a composite foil 7 a is adopted as shown in FIG. 8.

The constitution of the power semiconductor device 8 a used in thepresent embodiment is the same as that of the embodiment 1 shown in FIG.4. However, the constitution of the composite foil 7 a which is used forforming a metal joint section 7 in the case of die-mount-connecting apower semiconductor element 1 a with a lead frame 2 is not the one shownin FIG. 5A, but the one shown in FIG. 8 so that the present embodimentdiffers from the embodiment 1 in this respect.

In the present embodiment, the respective composite foils 7 a have theconstitutions of examples 11 through 15 as shown in Table 2. In cases ofexamples 11 through 15, each of 5 mm square power semiconductor elements1 a to which no mold has been applied are used as in the cases ofexamples 1 through 10.

Namely, in example 11, the composite foil 7 a applied is made of themetal layer 100 made from an Al layer having 100 μm layer thickness, andthe metal layer 130 made from an Au-20Sn layer being a high meltingpoint Pb-free solder having 20 μm layer thickness as shown in Table 2.In example 12, the composite foil 7 a applied is made of the metal layer100 made from a Zn layer having 100 μm layer thickness, and the metallayer 130 made from the Au-20Sn layer being the high melting pointPb-free solder having 20 μm layer thickness as shown in Table 2.

In example 13, the composite foil 7 a applied is made of the metal layer100 made from an Al layer having 100 μm layer thickness, and the metallayer 130 made from a Zn-6Al layer being a high melting point Pb-freesolder having 20 μm layer thickness as shown in Table 2. In example 14,the composite foil 7 a applied is made of the metal layer 100 made froma Cu/Invar alloy/Cu layer having 100 μm layer thickness, and the metallayer 130 made from the Au-20Sn layer being the high melting pointPb-free solder having 20 μm layer thickness as shown in Table 2. Inexample 15, the composite foil 7 a applied is made of the metal layer100 made from a Ti layer having 100 μm layer thickness, and the metallayer 130 made from the Au-20Sn layer being the high melting pointPb-free solder having 20 μm layer thickness as shown in Table 2.

With respect to the power semiconductor packages of examples 11 through15 wherein each of the composite foils 7 a having the above-describedconstitutions, 500 cycles each of temperature cycle tests of −55° C.(30min.)/150° C.(30 min.) are applied to twenty packages of each example asin the case of the above-described embodiment 1. As a result, no chipcrack did appear in all the examples 11 through 15 as indicated in Table2.

On the other hand, when the connection section is observed, cracksappear in an area of Al of less than 5% wherein the area extending fromthe end of Al to the connection section in the case where the metallayer 100 of Al in examples 11 and 13 functions to buffer thermalstress. FIG. 9 is a photograph, in section, showing the condition ofcracks in Al appeared in the case of example 11.

In the case of example 12 wherein the metal layer 100 is Zn, cracksappear in an area of Zn of less than 5% wherein the area extending fromthe end of Zn to the connection section. In the case of examples 14 and15 wherein the metal layer 100 is Cu/Invar alloy/Cu, and Ti having anintermediate thermal expansion coefficient in between Si and Cu, nocrack appears in any of Si, the solder, the Cu/Invar alloy/Cu, and Ti.FIG. 10 is a photograph, in section, showing the connection section inthe case of example 14. From the photograph, it is confirmed that thereis no crack in the metal layers 100 and 130 as well as on the Si side ofthe power semiconductor element 1 a.

From the fact as mentioned above in the present embodiment, it has beenfound that thermal stress due to the temperature cycles are buffered bymeans of the metal layer 100 of Al, Zn, the Cu/Invar alloy/Cu, and Ti toresults in no appearance of chip crack, so that sufficient connectionreliability can be obtained according to the present embodiment.

From the above results, it has been confirmed that when a stressbuffering layer is provided, a high-melting point Pb-free solder such asAu-20Sn which could not have been sufficiently used heretofore becauseof such reason that it can make to have a high melting point, but itturns into rigid and brittle on the other hand may be applied fordie-mount-connection. In addition, when the stress buffering layer isprovided, the Pb-free solder layer which contributes actually for theconnection may be made thinner, whereby the Au-20Sn can be inexpensivelyapplied.

Embodiment 3

As is apparent from the above embodiment 1, such a construction which isnot adversely affected, e.g. with appearance of cracks, by the rigid andbrittle connection layer 200 and the side of the power semiconductorelement 1 a connected with the connection layer 200, may be obtained bythe provision of the metal layer 100 wherein thermal stress is absorbedby the metal layer 100, even if the connection layer 200 comes to have ahigh melting point resulting in rigid and brittle characteristics.

In this connection, the present inventors get such an idea that when aBi, a Bi—Ag alloy, a Bi—Cu alloy, or a Bi—Ag—Cu alloy-based solder isused together with the metal layer 100, it becomes possible to use anyof these solders which could not have been used for thedie-mount-connection because of occurrence of cracks by applying itthinly in spite of requiring the thin connection thereof due to its lowthermal expansion coefficient of about 9 W/m·K, although there is nofear of the remelting in the case of the reflow by making it to have ahigh melting point.

More specifically, in the present embodiment, such a constitutionwherein Pb-free solder layers 130 with which a high melting point may beachieved are provided on the opposite surfaces of a metal layer 100 as acomposite foil 7 a is adopted as shown in FIG. 8.

The constitution of the power semiconductor device 8 a used in thepresent embodiment is the same as that of the embodiment 1 shown in FIG.4. However, the constitution of the composite foil 7 a which is used forforming a metal joint section 7 in the case of die-mount-connecting apower semiconductor element 1 a with a lead frame 2 is not the one shownin FIG. 5A, but the one shown in FIG. 8 so that the present embodimentdiffers from the embodiment 1 in this respect.

In the present embodiment, the respective composite foils 7 a have theconstitutions of examples 16 and 17 as shown in Table 2. In cases ofexamples 16 and 17, each of 5 mm square power semiconductor elements 1 ato which no mold has been applied are used as in the cases of examples 1through 10.

Namely, in example 16, the composite foil 7 a applied is made of themetal layer 100 made from an Al layer having 100 μm layer thickness, andthe metal layer 130 made from an Bi—Ag layer being a high melting pointPb-free solder having 20 μm layer thickness as shown in Table 2. Inexample 17, the composite foil 7 a applied is made of the metal layer100 made from a Cu/Invar alloy/Cu layer having 100 μm layer thickness,and the metal layer 130 made from the Bi layer being the high meltingpoint Pb-free solder having 20 μm layer thickness as shown in Table 2.

From the above results, it has been confirmed that when a stressbuffering layer is provided, the Bi-, the Bi—Ag alloy-, the Bi—Cualloy-, or the Bi—Ag—Cu alloy-based high-melting point Pb-free solderswhich could not have been sufficiently used heretofore because of thelow coefficients of thermal expansion may be applied fordie-mount-connection.

Embodiment 4

In the present embodiment, the constitution of a composite foil 7 a usedfor a metal joint section 7 of die-mount-connection with respect to alead frame 2 of a power semiconductor element 1 a adopts the sameconstitution as that of the above-described embodiment 1, but a powersemiconductor device 8 b (8) is constituted in a structure wherein astrap is used as shown in FIGS. 11A and 11B.

Namely, the power semiconductor device 8 b is manufactured in accordancewith the manufacturing process as described hereunder. The powersemiconductor element 1 a wherein the rear surface metallization isTi/Ni/Au is die-mount-connected by the use of the composite foil 7 aonto a Cu-based drain 9. Then, an electrode formed on the upper surfaceof the semiconductor element 1 a is connected with a lead 5 functioningas the source and the gate by using the composite foil 7 a and the Custrap 10. After connecting the strap, they are maintained at 350° C. for10 minutes, whereby the solder of the metal layer 120 of 260° C. orlower melting point is allowed to react with the metal of the metallayer 110 of 260° C. or higher melting point which constitute thecomposite foil 7 a as shown in FIG. 5A to produce the complete compound,so that a connection layer 200 is made to have a high melting point.

Thus, in the power semiconductor device 8 b, the power semiconductorelement 1 a is connected with the drain 9 and the strap 10 by metaljoint sections 7 as well as the strap 10 is connected with the lead 5 bythe metal joint section 7, respectively, as shown in FIG. 11A.

The composite foil 7 a to be used is prepared in such that the metallayer 100 is made of an Al layer having a layer thickness of 100 μm, themetal layer 110 is made of Cu, the metal layer 120 is made of Sn, and alayer thickness of a combination of those of the metal layers 110 and120 is made to be 10 μm as in example 18 shown in table 2. Then, thepower semiconductor element 1 a, the Cu strap 10, and the metal jointsection 7 are sealed with the use of an epoxy-based resin 6 to fabricatethe power semiconductor device 8 b.

With respect to twenty power semiconductor packages wherein each of themuses the power semiconductor device 8 b having the above-describedconstitution, a temperature cycle test for 500 cycles of −55° C.(30min.)/150° C.(30 min.) was implemented as in the case of theabove-described embodiment 1. As a result, no chip crack appeared inexample 18 as indicated in Table 2. When the connection section isobserved, cracks did appear in an area of Al, functioning to bufferthermal stress, of less than 5% wherein the area extending from the endof Al to the connection section.

From the fact as mentioned above, it has been found that thermal stressdue to the temperature cycles are buffered by means of the metal layer100 of Al in also the constitution of the power semiconductor device 8 bhaving the structure wherein the strap is used as shown in FIG. 11, sothat sufficient connection reliability can be obtained according to thepresent embodiment.

Embodiment 5

Although the case where a Cu-based material having a large thermalexpansion coefficient difference from that of Si in a semiconductorelement 1 is used as a lead frame 2 has been described in theabove-described embodiments 1 and 2, such verification is conducted inthe present embodiment that an application of the present invention ispossible with respect to a Fe-42Ni material as an iron (Fe group) alloyhaving a small thermal expansion coefficient difference, on thecontrary.

Namely, a power semiconductor device 8 a was fabricated by employing a42-alloy frame in accordance with the same manner as that mentioned inthe above-described embodiment 1. More specifically, it corresponds tothe one wherein the lead frame 2 in the power semiconductor device 8 ahaving the constitution shown in FIG. 4 is made from the 42-alloy, andthe other parts of the constitution are the same as that of example 1 inthe above-described embodiment 1.

The composite foil 7 a to be used is prepared as in the case of example1 in such that the metal layer 100 is made of an Al layer having a layerthickness of 100 μm, the metal layer 110 is made of Cu, the metal layer120 is made of Sn, and a layer thickness of a combination of those ofthe metal layers 110 and 120 is made to be 10 μm as in example 19 shownin table 2.

A semiconductor package is formed by using the power semiconductordevice 8 a having the constitution shown in FIG. 4 which is obtained asa result of the die-mount-connection wherein the composite foil 7 ahaving the above-described constitution is interposed between the powersemiconductor element 1 a and the lead frame 2 made of the 42-alloy, andthey are maintained at a heating temperature of 350° C. for a holdingtime of 10 minutes while keeping the interposed condition.

With respect to twenty power semiconductor packages each being obtainedby the use of the power semiconductor element 8 a having theabove-described constitution, a temperature cycle test for 500 cycles of−55° C.(30 min.)/150° C.(30 min.) was implemented as in the case of theabove-described embodiment 1. As a result, no crack appeared in the chipand the connection part in example 19 as indicated in Table 2.

Moreover, although there is no indication in Table 2, the compositefoils 7 a having the same constitutions as that of examples 2 through 10were used to fabricate the power semiconductor devices 8 a. Thetemperature cycle test was conducted with respect to twentysemiconductor packages wherein the power semiconductor devices 8 a asdescribed above were used. As a result, no chip crack was observed withrespect to all the packages.

From the fact as described above, it has been found that the presentinvention exhibits sufficient connection reliability with respect to notonly a Cu-based frame having a large thermal expansion coefficientdifference from that of Si, but also a lead frame having a small thermalexpansion coefficient difference from that of Si.

COMPARATIVE EXAMPLE 1

In the comparative example 1, unlike the present invention, a powersemiconductor device 8 a having the constitution as shown in FIG. 4 wasfabricated by the use of a Pb-5Sn solder having 20 μm layer thicknesswithout employing a composite foil 7 a containing a metal layer 100exerting stress buffering function.

With respect to twenty power semiconductor packages each being obtainedby the use of the power semiconductor element 8 a having theabove-described constitution, a temperature cycle test for 500 cycles of−55° C.(30 min.)/150° C.(30 min.) was implemented in accordance with thesame manner as that of examples 11 through 15.

As indicated in Table 2, no chip crack appeared in comparativeexample 1. However, when the connection section is observed, cracksappeared in an area of the Pb-5Sn solder of about 10% wherein the areaextending from the end of the Pb-5Sn solder to the connection section.From such result, it has been found that the load due to thermal stressdecreases with respect to the chip because of the flexiblecharacteristic of the solder.

COMPARATIVE EXAMPLE 2

In the comparative example 2, a composite foil having 20 μm thicknessmade of a Cu layer corresponding to the metal layer 110 and a Sn layercorresponding to the metal layer 120 without providing a constitutioncorresponding to the metal layer 100 is formed. The metallic foilconstituted into such composite foil as described above is interposedbetween a power semiconductor element 1 a on the side which has beenmetallized and a Cu lead frame 2, and die-mount-connection is conductedat 350° C. for holding 10 minutes in accordance with the same manner asthat mentioned in the above-described examples 1 through 10 to fabricatea power semiconductor device 8 a.

With respect to twenty power semiconductor packages each being obtainedby the use of the power semiconductor element 8 a thus fabricated, atemperature cycle test for 500 cycles of −55° C.(30 min.)/150° C.(30min.) was implemented. As a result, cracks appeared in the chip and theCu—Sn compound in a ratio of 6/20 as indicated in comparative example 2of Table 2. This is because all the connection part formed with the useof the composite foil is made of the Cu—Sn compound, whereby theconnection part becomes rigid and brittle, so that the thermal stressdue to the temperature cycle cannot be buffered thereby.

Namely, it is considered that the metal layer 100 exerting stressbuffering functions is not provided in the comparative example 2 unlikethe present invention, so that the cracks appeared. This result may be akind of such proof that the metal layer 100 exerting the stressbuffering function in the present invention acts effectively forpreventing the appearance of chip cracks, on the one hand.

COMPARATIVE EXAMPLE 3

In the comparative example 3, a composite foil 7 a containing a metallayer 100 exerting stress buffering function is not used unlike thepresent invention, but an Au-20Sn solder having 20 μm layer thickness isused to fabricate the power semiconductor device 8 a having theconstitution shown in FIG. 4. With respect to twenty power semiconductorpackages each being obtained by the use of the power semiconductordevice 8 a thus fabricated, a temperature cycle test for 500 cycles of−55° C.(30 min.)/150° C.(30 min.) was implemented. As a result, cracksappeared in the chip and the connection part in a ratio of 5/20 asindicated in comparative example 3 of Table 2. In this respect, it isconsidered that since the Au-20Sn solder is a hard solder, the thermalstress due to temperature cycle cannot be buffered in the connectionsection, whereby the load increases with respect the chip.

FIG. 12 shows an example of the chip cracks appeared. The case of FIG.12 is in such that wherein a 5 mm square power semiconductor device 8 aaccompanied with no mold is die-mount-connected to a Cu lead frame withan Au-20Sn solder in 20 μm layer thickness at 350° C. for 10 minuteholding time. Thereafter, the resulting product is subjected totemperature recycle test.

Embodiment 6

In the embodiments 1 through 5, the connection layers 200 having thesame constitutions and functioning as the stress buffering layers areformed on the semiconductor element side 1 and the side of the leadframe 2 of the metal layer 100 in the metal joint section 7 forconnecting the semiconductor element 1 such as the power semiconductorelement 1 a with the substrate such as the lead frame 2 in thesemiconductor device 8 such as the power semiconductor device 8 a asshown in FIG. 5B.

In the present embodiment, unlike the case of FIG. 5B, the case whereina metal layer functioning as the stress buffering layer 100 issandwiched in between a connection layer 210 and another connectionlayer 220 being different from one another in a metal joint section 7 asshown in FIG. 13A will be described. The constitution described in thepresent embodiment may be applied to the power semiconductor devices 8 aand 8 b the constitutions thereof are shown, for example, in FIGS. 4 and11, respectively, described in the embodiments 1 through 5.

Namely, roughly speaking, the constitutions described in the embodiments1 through 5 differ from the constitution which will be describedhereunder in the present embodiment 6 in that those of the connectionlayers formed on the opposite sides of the metal layer 100 constitutingthe metal joint section 7 are the same as or different from one anotherin the above-described both embodiments to be compared with each other.

The semiconductor device 8 applied in the present embodiment isconstituted into the power semiconductor device 8 a as shown in FIG. 4.More specifically, in the power semiconductor device 8 a, thesemiconductor element 1 being the power semiconductor element 1 a isdie-mount-connected onto the lead frame 2 through the metal jointsection 7. The metal joint section 7 is formed in such that a compositefoil 7 c for forming the joint section shown in FIG. 13B is placed on adie pad of the lead frame 2, furthermore, the power semiconductor device8 a is placed on the composite foil 7 c, and they are heated whilemaintaining the existing condition.

The rear surface on the silicon (Si) side of the power semiconductorelement 1 a being in contact with the composite foil 7 c is metallizedwith Ti/Ni/Au to assure the wettability. Also, the leas frame 2 is, forexample, copper(Cu)-based material having good coefficient of thermalconductivity. The power semiconductor element 1 a and the lead frame 2having the constitution as mentioned above is joined by means of themetal joint section 7 which is formed by such a manner that theinterposed composite foil 7 c is heated at a predetermined temperaturein the case of the die-mount-connection to be melted and solidified.

In the composite foil 7 c for forming the metal joint section 7, a metallayer 140 on a high melting point side made of a Pb-free solder having amelting point of 260° C. or higher to 400° C. or lower and forming aconnection layer 210 on the semiconductor element side 1 is provided oneither side of the metal layer 100 having a high melting point of 260°C. or higher as shown schematically in FIG. 13B. On the other side ofthe metal layer 100, a metal layer 150 on a low melting point side madeof a Pb-free solder forming a connection layer 220 on the side of thelead frame 2, having a melting point of 260° C. or higher to 400° C. orlower, and the melting point of which is lower than that of the highmelting point Pb-free solder forming the metal layer 140 is provided.

The composite foil 7 c having the constitution as described above isused to metal-join the semiconductor element 1 constituted in the formof the power semiconductor element 1 a to the substrate constituted inthe form of the lead frame 2, whereby the semiconductor deviceconstituted in the form of the power semiconductor device 8 a shown inFIG. 4 is manufactured. Such manufacturing process will be describedhereinbelow. The details of the process in the manufacturing method areschematically shown in FIGS. 14A to 14G.

Namely, as shown in FIGS. 14A and 14B, a metal layer 140 on a highmelting point side of the composite foil 7 c is held by a mounter 300,while a metal layer 150 on a low melting point side is supplied onto thelead frame 2 heated by a heater. In this case, the composite foil 7 c ispressed and scrubbed at a temperature at which only the metal layer 150on the low melting point side of the composite foil 7 c is melted asshown in FIG. 14C, whereby the composite foil is supplied while allowingit to be closely in contact with the lead frame 2 and evacuating voidsat the same time.

Thereafter, the composite foil 7 c is heated up to a temperature atwhich the metal layer 140 on the high melting point side is melted, andthe semiconductor element 1 as the power semiconductor element 1 a therear metallization of which is Ti/Ni/Au is supplied onto the metal layer140 by means of a mounter 310 as shown in FIG. 14D. In this case, thepower semiconductor element 1 a is supplied while pressing and scrubbingit as shown in FIG. 14E, whereby wettability in the connection part isassured and voids are evacuated at the same time.

In the power semiconductor element 1 a die-mount-connected by means ofthe metal joint section 7 which is made to have a high melting point,then, an electrode formed on the upper surface of the powersemiconductor element 1 a is bonded to leads 5 with the use of Au wires4, respectively, as shown in FIG. 14F. Furthermore, the powersemiconductor element 1 a, the lead frame 2, the metal joint section 7,and the wires 4 are sealed by using an epoxy-based resin 6, whereby thesemiconductor device 8 constituted in the form of the semiconductordevice 8 a is manufactured as shown in FIG. 14G.

In the semiconductor device 8 having the constitution as describedabove, compositions of the metal layers 100, 140, and 150 constitutingthe composite foil 7 c are variously changed, and effectiveness in theconstitutions of the present embodiment are verified. The results of theverification are shown in examples 20 to 23 of Table 2.

The composite foils 7 c constituted in the conditions described inexamples 20 to 23 of Table 2 are used to fabricate power semiconductorpackages in accordance with the process as described above. With respectto twenty power semiconductor packages each in the respective examples,a temperature cycle test for 500 cycles of −55° C.(30 min.)/150° C.(30min.) was implemented. Concerning the conditions of chip cracks, no chipcrack appeared in all of the examples 20 to 23 as indicated in Table 2.

When the connection section of the metal joint section 7 is observed,cracks appeared in an area of Al of less than 5% wherein the areaextending from the end of Al to the connection section in the case wherethe metal layer 100 of Al in examples 20, 22 and 23 functions to bufferthermal stress. On the other hand, when the connection section isobserved in the case where the metal layer is a Cu/Invar alloy/Cu inexample 21 having an intermediate thermal expansion coefficient of Siand Cu, no crack appeared on any of Si, in the metallic compounds, andin the Cu/Invar alloy/Cu. The thermal stress due to the temperaturecycles is buffered by means of the metal layer 100 in Al and theCu/Invar alloy/Cu. As a result, it is supposed that the appearance ofchip cracks can be prevented.

Although there is not indicated in Table 2, the test, wherein the metallayers 100, 140, and 150 constituting the composite foil 7 c arevariously changed, was conducted by the present inventors. It has beenfound from the results obtained by the above-described test incombination with the results shown in examples 20 to 23 in Table 2 thatthe connection layer 210 formed on the semiconductor element side of themetal layer 100 having a function to act as a stress buffering layer isconstituted by a Pb-free solder layer of Au—Sn-based alloys, Au—Ge-basedalloys, Au—Si-based alloys, Zn—Al-based alloys, Zn—Al—Ge-based alloys,Bi, Bi—Ag-based alloys, Bi—Cu-based alloys, Bi—Ag—Cu-based alloys andthe like alloys each having a melting point of 260° C. or higher to 400°C. or lower, while the connection layer 220 formed on the lead frameside of the metal layer 100 functioning as a stress buffering layer ismade to have a constitution made of a Pb-free solder having a lowermelting point than that of the connection layer 210 of 260° C. or higherto 400° C. or lower, whereby a die-mount-connection by which sufficientconnection reliability can be assured is achieved without accompanyingappearance of any chip crack by applying these Pb-free solders.

Moreover, the die-mount-connection wherein the composite foil 7 cdescribed in the present embodiment was effective in the case where thedie-mount-connection is applied to the semiconductor device 8 such asthe power semiconductor device 8 b and the like having the strap typestructure shown in FIG. 11.

Embodiment 7

In the constitution described in the present embodiment 7, connectionlayers 230 and 240 which differ from one another are formed on theopposite sides of a metal layer 100 having a stress buffering functionin a metal joint section 7 for joining a power semiconductor element 1 ato a lead frame 2 being the substrate as shown in FIG. 15A as in thecase of the above-described embodiment 6. The constitution of thepresent embodiment may be applied to the power semiconductor devices 8 aand 8 b having their constitutions shown, for example, in FIGS. 4 and11, respectively, as in the case of the above-described embodiment 6.

Such metal joint section 7 as described above is formed by using acomposite foil 7 d as shown in FIG. 15B. The composite foil 7 d isconstituted in such that a metal layer 160 made of a Pb-free solderhaving a melting point of 260° C. or higher to 400° C. or lower isprovided on the side where the metal layer 100 having functions of astress buffering layer is to be connected with the semiconductor element1, while a metal layer 170 made of a Pb-free solder having a meltingpoint of 260° C. or lower which forms an intermetallic compound with ametal is provided on the side where the metal layer 100 is to beconnected with the lead frame 2 as shown in FIG. 15B.

The semiconductor device 8 to which the present embodiment is to beapplied is the one which is constituted in the form of the powersemiconductor device 8 a as shown, for example, in FIG. 4. In the powersemiconductor device 8 a, the semiconductor element 1 being the powersemiconductor element 1 a is die-mount-connected on the lead frame 2through the metal joint section 7. The metal joint section 7 is formedby heating respective components in a condition wherein a composite foil7 d shown in FIG. 15B for forming the joint section is disposed on a diepad of the lead frame 2, and further the power semiconductor device 8 ais disposed on the composite foil 7 d.

For instance, the rear surface being in contact with the composite foil7 d on the silicon (Si) side of the power semiconductor element 1 a ismetallized with Ti/Ni/Au to assure the wettability. The lead frame 2 is,for example, made of a material of a copper (Cu)-based material havinggood coefficient of thermal conductivity. The power semiconductorelement 1 a and the lead frame 2 having such constitution as describedabove are joined with the metal joint section 7 formed by such a mannerthat the composite foil 7 d interposed between the power semiconductorelement 1 a and the lead frame 2 is heated at a predeterminedtemperature to melt and solidify in the case of thedie-mount-connection.

In the present embodiment, the power semiconductor device 8 a having theconstitution as described above can be manufactured as follows. Namely,as shown in FIGS. 14A and 14B, the side of the metal layer 160 of thecomposite foil is held by a mounter 300, while the side of the metallayer 170 is supplied onto the lead frame 2 heated by a heater. In thiscase, the composite foil is pressed and scrubbed at a temperature atwhich only the metal layer 170 on the low melting point side of thecomposite foil is melted as shown in FIG. 14C, whereby the compositefoil is supplied while allowing it to be closely in contact with thelead frame 2 and evacuating voids at the same time.

It is to be noted that a reference numeral, e.g. 160 and the likerelating to the composite foils 7 d and 7 e are indicated by putting itin parentheses so as not to confuse with those relating to the compositefoil 7 c in FIGS. 14A through 14G.

Thereafter, the composite foil 7 d is heated up to a temperature atwhich the high melting point metal layer 160 side is melted, and thesemiconductor element 1 its rear metallized with Ti/Ni/Au is suppliedonto the metal layer by means of a mounter 310 as shown in FIG. 14D. Inthis case, the power semiconductor element 1 is supplied while pressingand scrubbing it as shown in FIG. 14E, whereby wetness is assured andvoids are evacuated at the same time. After the die-mount-connection,the resulting product is held at 350° C. for 10 min., whereby the metalhaving a melting point of 260° C. or lower is allowed to react with themetal having a melting point of 260° C. or higher to make the connectionlayer to be an intermetallic compound so that a high melting point isattained in the resulting metallic compound.

In the power semiconductor element 1 die-mount-connected by means of themetal joint section 7 which is made to have a high melting point, then,an electrode formed on the upper surface of the power semiconductorelement 1 is bonded to leads 5 using Au wires 4 as shown in FIG. 14F.Furthermore, the power semiconductor element 1 a, the lead frame 2, themetal joint section 7, and the wire 4 are sealed by using an epoxy-basedresin 6 as shown in FIG. 14G. As a result of applying theabove-described process, the semiconductor device 8 is manufactured.

For the power semiconductor package thus fabricated in this manner, asindicated in examples 24 and 25 of Table 2, to twenty packages each ofthese conditions a temperature cycle test for 500 cycles of −55° C.(30min.)/150° C.(30 min.) was implemented. Concerning the conditions inappearance of chip cracks, no chip crack appeared in all of the examples24 and 25 as indicated in Table 2.

When the sectional view of the connection is observed, no crack appearedin any of Si, in the metallic compounds, and in the Cu/Invar alloy/Cu.It was found that the thermal stress due to the temperature cycles isbuffered by means of the metal layer in the Cu/Invar alloy/Cu, so thatthe metal joint section 7 has sufficient connection reliability.

Although there is not indicated in Table 2, the test wherein the metallayers 100, 160, and 170 constituting the composite foil 7 d arevariously changed was conducted by the present inventors. It was foundfrom the results obtained by the above-described test in combinationwith the results shown in examples 24 and 25 in Table 2 that theconnection layer 230 formed on the semiconductor element side of themetal layer 100 having a function to act as a stress buffering layer isconstituted by a Pb-free solder layer of such as Au—Sn-based alloys,Au—Ge-based alloys, Au—Si-based alloys, Zn—Al-based alloys,Zn—Al—Ge-based alloys, Bi, Bi—Ag-based alloys, Bi—Cu-based alloys,Bi—Ag—Cu-based alloys having a melting point of 260° C. or higher to400° C. or lower, while the connection layer 240 formed on the leadframe side of the metal layer 100 functioning as a stress bufferinglayer is made to have a constitution made of an intermetallic compoundhaving a melting point of 260° C. or higher which is formed by thereaction of one of Sn, In, Sn—Ag-based, Sn—Cu-based, Sn—Ag—Cu-based,Sn—Zn-based, Sn—Zn—Bi-based, Sn—In-based, In—Ag-based, In—Cu-based,Bi—Sn-based, Bi—In-based and the like Pb-free solders having a meltingpoint of 260° C. or lower with at least one of metals of Cu, Ag, Ni, andAu at the time of die-mount-connection, whereby the die-mount-connectionby which sufficient connection reliability can be assured is achievedwithout accompanying appearance of any chip crack by applying thesePb-free solders.

Moreover, the die-mount-connection wherein the composite foil 7 ddescribed in the present embodiment was effective in the case where thedie-mount-connection is applied to the semiconductor device 8 such asthe power semiconductor device 8 b having the strap type structure shownin FIG. 11.

Embodiment 8

In the configuration described in a present embodiment 8, in a metaljoint section 7 for joining a power semiconductor element 1 a to a leadframe 2 being the substrate, as in the case of the above-describedembodiment 6, connection layers 250 and 260 which differ from oneanother are formed sandwiching a metal layer 100 having a stressbuffering function, as shown in FIG. 16A. The configuration of thepresent embodiment may be applied to the power semiconductor devices 8 aand 8 b having their configurations shown, for example, in FIGS. 4 and11, respectively, as in the case of the above-described embodiment 6.

Such metal joint section 7 is formed by using a composite foil 7 e asshown in FIG. 16B. The composite foil 7 e is configured to have a metallayer 180 made of a Pb-free solder having a melting point of 260° C. orlower and a metal having a melting point of 260° C. or higher providedon the side where the metal layer 100 having stress buffering function alayer is connected with the semiconductor element, and a metal layer 190made of a Pb-free solder having a melting point lower than that of themetal layer 180 and a metal having a melting point of 260° C. or higherprovided on the side where the metal layer 100 is connected with thelead frame 2, as shown in FIG. 16B.

The metal layer 180 is configured, as shown in FIG. 16B, such that ametal layer 180 a having a melting point of 260° C. or higher isprovided on the upper surface of the metal layer 100, and a metal layer180 b made of a Pb-free solder having a melting point of 260° C. orlower is further laminated on the metal layer 180 a. The metal layer 190is also configured, as shown in FIG. 16B, such that a metal layer 190 ahaving a melting point of 260° C. or higher is provided on the uppersurface of the metal layer 100, and a metal layer 190 b having a meltingpoint of 260° C. or lower made of a Pb-free solder having a lowermelting point than that of the Pb-free solder composing the metal layer180 b is further laminated on the metal layer 190 a.

In the configuration shown in FIG. 16B, the laminated structure of themetal layer 180 is configured by the metal layers 180 a and 180 b, andthe metal layer 190 is configured by the metal layers of 190 a and 190b. However, the reason for the arrangement of such configuration is inthat the metal layer 180 a reacts with the metal layer 180 b, while themetal layer 190 a reacts with the metal layer 190 b, respectively, atthe time when the composite foil 7 e is applied fordie-mount-connection, whereby the intermetallic compounds each having amelting point of 260° C. or higher are obtained.

An example of such constitution of the composite foil 7 e isexemplified, for example, in examples 26 and 27 in Table 2. In the caseof example 26, the composite foil 7 e is constituted by using, Cu as themetal layer 180 a, Sn as the metal layer 180 b, Al as the metal layer100, Cu as the metal layer 190 a, and In-48Sn as the metal layer 190 b,respectively, wherein a total layer thickness of the metal layers 180 aand 180 b is 10 μm, a layer thickness of the metal layer 100 is 100 μm,and a total layer thickness of the metal layers 190 a and 190 b is 10μm.

Similarly, in the case of example 27, the composite foil 7 e isconstituted by using, Ag as the metal layer 180 a, Sn as the metal layer180 b, Al as the metal layer 100, Ag as the metal layer 190 a, andSn-9Zn as the metal layer 190 b, respectively, wherein a total layerthickness of the metal layers 180 a and 180 b is 20 μm, a layerthickness of the metal layer 100 is 100 μm, and a total layer thicknessof the metal layers 190 a and 190 b is 20 μm.

Furthermore, in the case where metal composition parts havingsubstantially the same functions as that of the metal layers 180 a and190 a are contained in the metal layer 100, the apparent constitutionmay be such that, although it is not shown, the metal layer 180 is madeof only the metal layer 180 b on the metal layer 100, while the metallayer 190 is made of only the metal layer 190 b on the metal layer 100.

Examples of such constitution as described above are indicated inexamples 28 to 30 of Table 2. Namely, in the case of example 28, thecomposite foil 7 e is constituted by using, Sn as the metal layer 180 b,Cu/Invar/Cu as the metal layer 100, and In-48Sn as the metal layer 190b, respectively, wherein a layer thickness of the metal layer 180 b is10 μm, a layer thickness of the metal layer 100 is 100 μm, and a layerthickness of the metal layer 190 b is 10 μm. However, in this case, theCu in the Cu/Invar/Cu has functions as that of the metal layers 180 aand 190 a shown in FIG. 16B.

Similarly, in the case of example 29, the composite foil 7 e isconstituted by using, Sn-3.5Ag as the metal layer 180 b, Cu/Invar/Cu asthe metal layer 100, and In-48Sn as the metal layer 190 b, respectively,wherein a layer thickness of the metal layer 180 b is 10 μm, a layerthickness of the metal layer 100 is 100 μm, and a layer thickness of themetal layer 190 b is 10 μm. However, in this case, the Cu in theCu/Invar/Cu functions to act as that of the metal layers 180 a and 190 ashown in FIG. 16B.

In the case of example 30, the composite foil 7 e is constituted byusing, Sn as the metal layer 180 b, Cu/Invar/Cu as the metal layer 100,and Sn-9Zn as the metal layer 190 b, respectively, wherein a layerthickness of the metal layer 180 b is 10 μm, a layer thickness of themetal layer 100 is 100 μm, and a layer thickness of the metal layer 190b is 10 μm. However, in this case, the Cu in the Cu/Invar/Cu functionsto act as that of the metal layers 180 a and 190 a shown in FIG. 16B.

The semiconductor device 8 to which the present embodiment is to beapplied is constituted in the form of, for example, the powersemiconductor device 8 a as shown in FIG. 4. In the power semiconductordevice 8 a, the semiconductor element 1 being the power semiconductorelement 1 a is die-mount-connected onto the lead frame 2 interposing themetal joint section 7 therebetween. The metal joint section 7 is formedby heating respective components in a condition wherein a composite foil7 e shown in FIG. 16B for forming the joint section is disposed on a diepad of the lead frame 2, and further the power semiconductor device 8 ais disposed on the composite foil 7 e.

For instance, the rear surface being in contact with the composite foil7 e on the silicon (Si) side of the power semiconductor element 1 a ismetallized with Ti/Ni/Au to assure the wettability. In addition, thelead frame 2 is, for example, made of a material of a copper(Cu)-basedmaterial having a good coefficient of thermal conductivity. The powersemiconductor element 1 a and the lead frame 2 having such constitutionas described above are joined to the metal joint section 7 formed bysuch a manner that the composite foil 7 e interposed between the powersemiconductor element 1 a and the lead frame 2 is heated at apredetermined temperature to melt and solidify at the time of thedie-mount-connection.

In the present embodiment, the power semiconductor device 8 a having theconstitution as described above can be manufactured as follows. That is,as shown in FIGS. 14A and 14B, a mounter 300 holds the side of the metallayer 180 where the melting point thereof is high of the composite foil,while the side of the metal layer 190 where the melting point thereof islow is supplied onto the lead frame 2 heated by a heater. At this time,the composite foil is pressed and scrubbed at a temperature at whichonly the metal layer 190 on the low melting point side of the compositefoil is melted, as shown in FIG. 14C, whereby the composite foil issupplied while allowing it to be closely in contact with the lead frame2 and evacuating voids at the same time.

Note that, a reference numeral, e.g. 180 and the like relating to thecomposite foils 7 d and 7 e are indicated by putting it in parenthesesso as not to confuse with those relating to the composite foil 7 c inFIGS. 14A through 14G.

Thereafter, the composite foil is heated up to a temperature at whichthe metal layer 180 on the high melting point side is melted, and thesemiconductor element 1 its rear metallization is Ti/Ni/Au is suppliedonto the metal layer by means of a mounter 310, as shown in FIG. 14D. Inthis case, the power semiconductor element 1 is supplied while pressingand scrubbing it as shown in FIG. 14E, whereby wettability is assuredand voids are evacuated at the same time. After thedie-mount-connection, the resulting product is held at 350° C. for 10min., whereby the metal having a melting point of 260° C. or lower isallowed to react with the metal having a melting point of 260° C. orhigher to make the connection layer to be an intermetallic compound sothat a high melting point is attained in the resulting metalliccompound.

In the power semiconductor element 1 die-mount-connected by means of themetal joint section 7 which is made to have a high melting point, then,an electrode formed on the upper surface of the power semiconductorelement 1 is bonded to leads 5 using Au wires 4, respectively, as shownin FIG. 14F. Furthermore, the power semiconductor element 1 a, the leadframe 2, the metal joint section 7, and the wires 4 are sealed by usingan epoxy-based resin 6 as shown in FIG. 14G. As a result of applying theabove-described process, the semiconductor device 8 is manufactured.

For the power semiconductor package thus fabricated in this manner, asindicated in examples 26 through 30 of Table 2, to twenty packages eachof these conditions a temperature cycle test for 500 cycles of −55°C.(30 min.)/150° C.(30 min.) was implemented. Concerning the conditionsin appearance of chip cracks, no chip crack appeared in all of theexamples 26 through 30 as indicated in Table 2.

When the sectional view of the connection is observed, cracks areappeared in the Al area which is less than 5% from the edge of Al to theconnection section. As a result, it has been found that the thermalstress due to the temperature cycles is buffered by means of the metallayer of Al, so that the metal joint section 7 has sufficient connectionreliability.

Although there is not indicated in Table 2, the test wherein the metallayers 100, 180 (180 a, 180 b), and 190 (190 a, 190 b) constituting thecomposite foil 7 e are variously changed was conducted by the presentinventors. It was found from the results obtained by the above-describedtest in combination with the results shown in examples 29 through 30 inTable 2 that the connection layer 250 formed on the semiconductorelement side of the metal layer 100 having a function as a stressbuffering layer is made to have a constitution made of an intermetalliccompound having a melting point of 260° C. or higher which is formed bythe reaction of one of such as Sn, In, Sn—Ag-based, Sn—Cu-based,Sn—Ag—Cu-based, Sn—Zn-based, Sn—Zn—Bi-based, Sn—In-based, In—Ag-based,In—Cu-based, Bi—Sn-based, Bi—In-based Pb-free solders having a meltingpoint of 260° C. or lower with at least one of metals of Cu, Ag, Ni, andAu at the time of die-mount-connection, while the connection layer 260formed on the lead frame side of the metal layer 100 functioning as astress buffering layer is made to have a constitution made of anintermetallic compound having a melting point of 260° C. or higher whichis formed by the reaction of one of such as Sn, In, Sn—Ag-based,Sn—Cu-based, Sn—Ag—Cu-based, Sn—Zn-based, Sn—Zn—Bi-based, Sn—In-based,In—Ag-based, In—Cu-based, Bi—Sn-based, Bi—In-based Pb-free soldershaving a lower melting point than that of the Pb-free solder forming theconnection layer 250 with at least one of metals of Cu, Ag, Ni, and Auat the time of die-mount-connection, whereby the die-mount-connection bywhich sufficient connection reliability can be assured is achievedwithout accompanying appearance of any chip crack by applying thesePb-free solders.

Moreover, the constitutions described in examples 31 and 32 of Table 2were also effective for the composite foil 7 e having the constitutionshown in FIG. 16B. The constitution of example 31 is exemplified Cu isused as the metal layer 180 a, Au-20Sn is used as the metal layer 180 b,Al is used as the metal layer 100, Cu is used as the metal layer 190 a,and Sn is used as the metal layer 190 b, respectively. It is designedthat a total layer thickness of the metal layers 180 a and 180 b is 20μm, a layer thickness of the metal layer 100 is 100 μm, and a totallayer thickness of the metal layers 190 a and 190 b is 20 μm.

The constitution of example 32 is exemplified such that Cu is used asthe metal layer 180 a, Bi is used as the metal layer 180 b, Al is usedas the metal layer 100, Cu is used as the metal layer 190 a, and Sn isused as the metal layer 190 b, respectively, wherein a total layerthickness of the metal layers 180 a and 180 b is 10 μm, a layerthickness of the metal layer 100 is 100 μm, and a total layer thicknessof the metal layers 190 a and 190 b is 10 μm.

Furthermore, the die-mount-connection wherein the composite foil 7 e isused described in the present embodiment was effective in the case wherethe die-mount-connection is applied to the semiconductor device 8 suchas the power semiconductor device 8 b having the strap type structureshown in FIG. 11.

Embodiment 9

In the embodiments 1 through 8, it is described that the metal jointwithout accompanying appearance of any chip crack can be conducted byproviding the stress buffering layer. In this respect, the presentinventors studied points to keep in mind in the case of applying thecomposite foil 7 a and the like used in the metal joining in view ofmanufacturing point of view. In the case of executing the constitutionsshown in aforementioned embodiments 1 through 8, for example, any of thecomposite foils exemplified in Table 2 may be applied as describedabove. However, the metal joining with the use of such composite foil asdescribed above is proposed for the first time by the present invention.Accordingly, it is very important for actually applying the invention ofthe present application that the points to keep in mind in the actualmanufacturing stage are studied dissimilar the case where there are anumber of long succession of practical knowledge in the actualmanufacturing stage as in the conventional configurations.

In view of the fact that the present invention has been made forassuring connection reliability of a high degree, the present inventorsstudied factors for affecting connection reliability in the case ofemploying particularly the composite foil. As a result, it has beenfound that the connection reliability is remarkably affected with orwithout scrubbing in the case of supplying the composite foil at thetime of die-mount-connection.

Table 3 indicates cases of examples 10 and 28 shown in Table 2 withrespect to influences upon poor connection after the connection with orwithout scrubbing in the case of metal-joining with the use of thecomposite foil at the time of die-mount-connection.

TABLE 3 Pressurizing/ Pressurizing/ Scrubbing at Number of Scrubbing atSupplying Appearance Composition of Supplying Semiconductor Connectionof Poor No. Die-Mount-Connection Part Composite Foil Element TemperatureConnection 1 Sn/(Cu/Inver/Cu)/Sn = 10 μm/ No No 400° C. 10/20  100 μm/10μm 2 Sn/(Cu/Inver/Cu)/Sn = 10 μm/ No Yes 400° C. 3/20 100 μm/10 μm 3Sn/(Cu/Inver/Cu)/Sn = 10 μm/ Yes Yes 400° C. 0/20 100 μm/10 μm 4Sn/(Cu/Inver/Cu)/In—48Sn = 10 μm/ Yes Yes 400° C. 0/20 100 μm/10 μm

In the case of manufacturing a semiconductor package with the use of acomposite foil, the procedure is such that, first the composite foil issupplied on a lead frame to join the composite foil to the lead frame,and then, a semiconductor element is supplied onto the composite foiljoined to the lead frame to join the semiconductor element to thecomposite foil. In such procedure as described above, a timing forapplying the scrubbing is considered to be in the case of supplying thecomposite foil onto the lead frame, or in the case of supplying thesemiconductor element onto the composite foil joined onto the leadframe. The present inventors studied on influences in both theabove-described cases with or without the scrubbing.

Table 3 indicates a condition with pressurizing/scrubbing, or acondition without pressurizing/scrubbing in the case of supplying thecomposite foil onto the lead frame (indicated by “Pressurizing/Scrubbingat supplying Composite Foil” in the table); and a condition withpressurizing/scrubbing, or a condition without pressurizing/scrubbing inthe case of supplying the semiconductor element onto the composite foiljoined onto the lead frame (indicated by “Pressurizing/Scrubbing atSupplying Semiconductor Element” in the table).

Table 3 indicates the number of appearance of poor connection after theconnection in both the cases of examples 10 and 28 in Table 2. Here,such a condition that a ratio of unconnected part, i.e. the presence ofvoids and unwet parts observed by means of ultrasonic flaw detection is20% or more is defined as the poor connection.

When no scrubbing is applied to both the cases of supplying thecomposite foil and the semiconductor element (indicated by No. 1 in thetable) in the semiconductor package of example 10 containing a metaljoint having an excellent constitution wherein no appearance of chipcrack is observed, poor connections appeared in the half of the samples.In this respect, however, when pressurizing/scrubbing is applied in onlythe case of supplying the semiconductor element, the poor connectionswere remarkably reduced as indicated by No. 2 of Table 3. Nevertheless,an appearance of poor connection was confirmed with respect to a part ofthe samples. Accordingly, when the pressurizing/scrubbing is applied inboth the cases of supplying the composite foil and the semiconductorelement (indicated by No. 3 in the table), it was confirmed that no poorconnection appeared.

Thus, as shown in the embodiments 1 through 5, it is desirable to applyat least pressurizing/scrubbing step to either case of supplying thecomposite foil or the case of supplying the semiconductor element in thedie-mounting wherein the composite foil which is prepared by providingthe metal layers having the same constitutions on the both sides ofmetal layer having stress buffering function is used. Besides, it hasbeen confirmed that it is very desirable to apply thepressurizing/scrubbing step to both the cases of supplying the compositefoil and supplying the semiconductor element.

The results as described above are also applicable for the case wherethe die-mounting wherein the composite foil which is prepared byproviding the metal layers having different constitutions from oneanother on the both sides of the other metal layer having stressbuffering function is applied as shown in the embodiments 6 through 8.In illustration of such results as described above, the number ofappearance of poor connection is shown in the Table 3, in theconstitution corresponding to example 28 of Table 2 wherein thepressurizing/scrubbing step is applied to both the cases of supplyingthe composite foil and supplying the semiconductor element. The numberof appearance of poor connection was decreased as compared with the casewhere no pressurizing/scrubbing step was applied and the case where thepressurizing/scrubbing step was applied to either the case of supplyingthe composite foil or the case of supplying the semiconductor element.

From the above-described results, it has been confirmed that when atemperature stratum is provided in the connection layer on the front andrear surfaces of a composite foil and the pressurizing/scrubbing stepsare applied to cases of supplying the composite foil and supplying thesemiconductor element, the connectability and the void evacuatabilitycan be improved.

In the foregoing, the invention made by the inventors of the presentinvention has been concretely described based on the embodiments.However, it is needless to say that the present invention is not limitedto the foregoing embodiments and various modifications and alterationscan be made within the scope of the present invention.

In other words, although the case where the invention is applied to thedie-mount-connection for a power semiconductor device has been describedas the exemplification, an applicable semiconductor device is notlimited to such power semiconductor device, but they may be the onesother than the power semiconductor device as long as they are to bedie-mount-connected. Examples of them include a diode for alternators,an IGBT substrate, a front-end module such as an RF module, a powermodule for automobiles.

In addition, in the above description, although such an example whereina semiconductor package employing a power semiconductor device isreflow-mounted onto the substrate has been described, the invention maybe applied to, for example, the case wherein an MCM (Multi Chip Module)configuration is used, as a matter of course.

In the above description, a laminated configuration wherein a metallayer 120 made of a metal having a low melting point of 260° C. or lowerand a metal layer 110 made of a metal having a high melting point of260° C. or higher are laminated on the metal layer 100 in such a mannerthat the low melting point metal layer 120 is positioned on the side ofa material to be connected has been described. However, it may bemodified such that a single layer having a constitution wherein themetal having a low melting point of 260° C. or lower exists mixedly withthe metal having a high melting point of 260° C. or higher is appliedwithin a range wherein wettability can be assured between the materialto be connected thereto. For example, both the metals may be nested in areticular pattern, or a row of the low melting point metal may beparalleled to a row of the high melting point metal in a staggeredpattern. It is sufficient that a connection layer 200 obtained by thereaction of the above-described both components and having a highmelting point of 260° C. or higher can be formed, as a result of heatingboth the components while maintaining a state wherein the wettabilitybetween the side of the material to be connected thereto is assured.

INDUSTRIAL APPLICABILITY

The present invention can be applied effectively to thedie-mount-connection for a semiconductor device represented by a powersemiconductor.

1. A semiconductor device wherein a semiconductor element is die-mount-connected onto a lead frame by means of a metal joint, characterized in that the metal joint includes: a stress buffering layer for buffering a thermal stress produced due to a thermal expansion coefficient difference between the lead frame and the semiconductor element; a connection layer formed on the semiconductor element side of the stress buffering layer and connecting the stress buffering layer with the semiconductor element; and another connection layer formed on the side of the lead frame of the stress buffering layer and connecting the stress buffering layer with the lead frame.
 2. The semiconductor device according to claim 1, characterized in that the connection layer is a metal layer or an intermetallic compound layer having a melting point of 260° C. or higher; and the stress buffering layer is a metal layer having a thermal expansion coefficient ranging from the thermal expansion coefficient of the semiconductor element to the thermal expansion coefficient of the lead frame.
 3. The semiconductor device according to claim 1, characterized in that the connection layer is a metal layer or an intermetallic compound layer having a melting point of 260° C. or higher; and the stress buffering layer is a metal layer having an yield stress of less than 100 MPa.
 4. The semiconductor device according to claim 1, characterized in that the connection layer formed on the semiconductor element side of the stress buffering layer is made of a Pb-free solder layer of an Au—Sn-based alloy, an Au—Ge-based alloy, an Au—Si-based alloy, a Zn—Al-based alloy, a Zn—Al—Ge-based alloy, Bi, a Bi—Ag-based alloy, a Bi—Cu-based alloy, a Bi—Ag—Cu-based alloy or the like having a melting point of 260° C. or higher to 400° C. or lower; and the connection layer formed on the side of the lead frame of the stress buffering layer is made of a Pb-free solder layer having a lower melting point than that of the connection layer formed on the semiconductor element side of the stress buffering layer of 260° C. or higher to 400° C. or lower.
 5. The semiconductor device according to claim 1, characterized in that the connection layer formed on the semiconductor element side of the stress buffering layer is made of a Pb-free solder layer of an Au—Sn-based alloy, an Au—Ge-based alloy, an Au—Si-based alloy, a Zn—Al-based alloy, a Zn—Al—Ge-based alloy, Bi, a Bi—Ag-based alloy, a Bi—Cu-based alloy, a Bi—Ag—Cu-based alloy or the like having a melting point of 260° C. or higher to 400° C. or lower; and the connection layer formed on the side of the lead frame of the stress buffering layer is made of an intermetallic compound layer having a melting point of 260° C. or higher and formed by the reaction of at least one of Sn, In, Sn—Ag-based, Sn—Cu-based, Sn—Ag—Cu-based, Sn—Zn-based, Sn—Zn—Bi-based, Sn—In-based, In—Ag-based, In—Cu-based, Bi—Sn-based, Bi—In-based and the like Pb-free solders with at least one metal of Cu, Ag, Ni, and Au in the case of the die-mount-connection.
 6. The semiconductor device according to claim 1, characterized in that the connection layer formed on the semiconductor element side of the stress buffering layer is made of an intermetallic compound layer having a melting point of 260° C. or higher and formed by the reaction of at least one of Sn, In, Sn—Ag-based, Sn—Cu-based, Sn—Ag—Cu-based, Sn—Zn-based, Sn—Zn—Bi-based, Sn—In-based, In—Ag-based, In—Cu-based, Bi—Sn-based, Bi—In-based and the like Pb-free solders each having a melting point of 260° C. or lower with at least one metal of Cu, Ag, Ni, and Au in the case of the die-mount-connection; and the connection layer formed on the side of the lead frame of the stress buffering layer is made of an intermetallic layer having a melting point of 260° C. or higher and formed by the reaction of at least one of Sn, In, Sn—Ag-based, Sn—Cu-based, Sn—Ag—Cu-based, Sn—Zn-based, Sn—Zn—Bi-based, Sn—In-based, In—Ag-based, In—Cu-based, Bi—Sn-based, Bi—In-based and the like Pb-free solders each having a lower melting point than that of the Pb-free solder forming the connection layer formed on the semiconductor element side of the stress buffering layer with at least one metal of Cu, Ag, Ni, and Au in the case of the die-mount-connection.
 7. A semiconductor device wherein a semiconductor element is die-mount-connected onto a lead frame by means of a metal joint, characterized in that: the metal joint contains an unreacted high melting point metal which does not react in the case of the die-mount-connection; and an intermetallic compound formed by the reaction in the case of joining the high melting point metal to the semiconductor element as well as joining the high melting point metal to the lead frame.
 8. A semiconductor device having a semiconductor element, and a substrate connected to the semiconductor element, characterized in that: the semiconductor element is connected with the substrate through a metal containing layer containing a metal and an intermetallic compound layer being thinner than the metal containing layer and including the metal component contained in the metal containing layer; and the connection between the semiconductor element and the substrate does not melt even at the heat-resistant upper limit of the semiconductor device.
 9. A semiconductor device having a semiconductor element, and a lead frame connected to the semiconductor element through a connection part, characterized in that: the connection part has a metal containing layer containing a metal and an intermetallic compound layer being thinner than the metal containing layer and including the metal component contained in the metal containing layer; and the connection part does not melt even at the heat-resistant upper limit of the semiconductor device.
 10. A semiconductor device wherein a semiconductor element is die-mount-connected onto a lead frame, then, the resulting product is subjected to wire-bonding, and resin-molding, characterized in that: the die-mount-connected part is composed successively of from the semiconductor element side, an intermetallic compound layer having a melting point of 260° C. or higher, a metallic compound layer having a melting point of 260° C. or higher, and another intermetallic compound layer having a melting point of 260° C. or higher in this order.
 11. The semiconductor device according to claim 10, characterized in that the intermetallic compound layer is formed by the reaction of at least one of Sn, In, Sn—Ag-based, Sn—Cu-based, Sn—Ag—Cu-based, Sn—Zn-based, Sn—Zn—Bi-based, Sn—In-based, In—Ag-based, In—Cu-based, Bi—Sn-based, and Bi—In-based Pb-free solders with at least one metal of Cu, Ag, Ni, and Au in the case of the die-mount-connection.
 12. A semiconductor device wherein a semiconductor element is die-mount-connected onto a lead frame, then, the resulting product is subjected to wire-bonding, and resin-molding, characterized in that: the die-mount-connected part is composed successively of from the semiconductor element side, a Pb-free solder layer having a melting point of 260° C. or higher to 400° C. or lower, a metallic compound layer having a melting point of 260° C. or higher, and another Pb-free solder layer having a melting point of 260° C. or higher to 400° C. or lower, in this order.
 13. The semiconductor device according to claim 12, characterized in that the Pb-free solder layer having a melting point of 260° C. or higher to 400° C. or lower is made of at least any one of Au—Sn-based alloys, Au—Ge-based alloys, Au—Si-based alloys, Zn—Al-based alloys, Zn—Al—Ge-based alloys, Bi, Bi—Ag-based alloys, Bi—Cu-based alloy, and Bi—Ag—Cu-based alloys.
 14. The semiconductor device according to claim 10, characterized in that the metal layer having a melting point of 260° C. or higher is made of at least one metal of Al, Mg, Ag, Zn, Cu, and Ni.
 15. The semiconductor device according to claim 10, characterized in that the metal layer having a melting point of 260° C. or higher is made of at least one member of Cu/Invar alloy/Cu composite materials, Cu/Cu₂O composite materials, Cu—Mo alloys, Ti, Mo, and W.
 16. A manufacturing method for a semiconductor device wherein a semiconductor element is die-mount-connected onto a lead frame by means of a metal joint, characterized by: heating a composite foil to form a metal joint in a condition wherein the composite foil is interposed between the semiconductor element and the lead frame to from the metal joint; the composite foil including a layer containing a metal having a melting point of 260° C. or lower and disposed on the semiconductor element side of a metal layer having a melting point of 260° C. or higher as well as another metal having a melting point of 260° C. or higher and disposed on the side of the lead frame of the metal layer, both the metals forming an intermetallic compound having a melting point of 260° C. or higher as a result of a reaction.
 17. The manufacturing method for a semiconductor device according to claim 16, characterized in that: the metal layer having a melting point of 260° C. or higher is formed from at least any one of Al, Mg, Ag, Zn, Cu, and Ni; the metal having a melting point of 260° C. or lower and forming an intermetallic compound having a melting point of 260° C. or higher as a result of the reaction is at least one of Sn, In, Sn—Ag-based, Sn—Cu-based, Sn—Ag—Cu-based, Sn—Zn-based, Sn—Zn—Bi-based, Sn—In-based, In—Ag-based, In—Cu-based, Bi—Sn-based, and Bi—In-based Pb-free solders; and the metal having a melting point of 260° C. or higher and forming an intermetallic compound having a melting point of 260° C. or higher as a result of the reaction is at least one metal of Cu, Ag, Ni, and Au. 